Sriseshan Srikanth

According to our database, Sriseshan Srikanth authored at least 15 papers between 2016 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems.

Bobin Deng, Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook

IEEE Trans. Computers, 2022

2021

SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads.

Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook

ACM Trans. Archit. Code Optim., 2021

2020

Energy efficient architectures for irregular data streams.

Sriseshan Srikanth

PhD thesis, 2020

MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams.

Sriseshan Srikanth, Anirudh Jain, Joseph M. Lennon, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook

ACM Trans. Archit. Code Optim., 2020

Intrepydd: performance, productivity, and portability for data science application kernels.

Tong Zhou, Jun Shirako, Anirudh Jain, Sriseshan Srikanth, Thomas M. Conte, Richard W. Vuduc, Vivek Sarkar

Proceedings of the 2020 ACM SIGPLAN International Symposium on New Ideas, 2020

2019

Experimental Insights from the Rogues Gallery.

Jeffrey S. Young, E. Jason Riedy, Thomas M. Conte, Vivek Sarkar, Prasanth Chatarasi, Sriseshan Srikanth

Proceedings of the 2019 IEEE International Conference on Rebooting Computing, 2019

2018

Extending Moore's Law via Computationally Error-Tolerant Computing.

Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank

ACM Trans. Archit. Code Optim., 2018

Tackling memory access latency through DRAM row management.

Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang

Proceedings of the International Symposium on Memory Systems, 2018

Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip.

Anirudh Jain, Sriseshan Srikanth, Erik P. DeBenedictis, Tushar Krishna

Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures.

Sriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017

The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing.

Sriseshan Srikanth, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook

Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C.

Erik P. DeBenedictis, Jeanine E. Cook, Sriseshan Srikanth, Thomas M. Conte

Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

2016

A Brief Survey of Non-Residue Based Computational Error Correction.

Sriseshan Srikanth, Bobin Deng, Thomas M. Conte

CoRR, 2016

Computationally-redundant energy-efficient processing for y'all (CREEPY).

Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook

Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Energy efficiency limits of logic and memory.

Sapan Agarwal, Jeanine E. Cook, Erik DeBenedictis, Michael P. Frank, Gert Cauwenberghs, Sriseshan Srikanth, Bobin Deng, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte

Proceedings of the IEEE International Conference on Rebooting Computing, 2016