Mengjie Mao

According to our database, Mengjie Mao authored at least 27 papers between 2010 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Exploring Applications of STT-RAM in GPU Architectures.

Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Helen Li, Yiran Chen

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2019

Thread Batching for High-performance Energy-efficient GPU Memory Design.

Bing Li, Mengjie Mao, Xiaoxiao Liu, Tao Liu, Zihao Liu, Wujie Wen, Yiran Chen, Hai (Helen) Li

ACM J. Emerg. Technol. Comput. Syst., 2019

2018

TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.

Zihao Liu, Mengjie Mao, Tao Liu, Xue Wang, Wujie Wen, Yiran Chen, Hai Li, Danghui Wang, Yukui Pei, Ning Ge

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

Cross-Layer Optimization for Multilevel Cell STT-RAM Caches.

Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Helen Li

IEEE Trans. Very Large Scale Integr. Syst., 2017

An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory.

Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai Li

IEEE Trans. Computers, 2017

2016

Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators.

Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Boxun Li, Yu Wang, Hao Jiang, Mark Barnell, Qing Wu, Jianhua Joshua Yang, Hai Li, Yiran Chen

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Heterogeneous systems with reconfigurable neuromorphic computing accelerators.

Sicheng Li, Xiaoxiao Liu, Mengjie Mao, Hai (Helen) Li, Yiran Chen, Boxun Li, Yu Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations.

Wujie Wen, Mengjie Mao, Hai Li, Yiran Chen, Yukui Pei, Ning Ge

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache.

Xue Wang, Mengjie Mao, Enes Eken, Wujie Wen, Hai Li, Yiran Chen

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

TEMP: thread batch enabled memory partitioning for GPU.

Mengjie Mao, Wujie Wen, Xiaoxiao Liu, Jingtong Hu, Danghui Wang, Yiran Chen, Hai Li

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

The applications of memristor devices in next-generation cortical processor designs.

Hai Li, Beiye Liu, Xiaoxiao Liu, Mengjie Mao, Yiran Chen, Qing Wu, Qinru Qiu

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications.

Mengjie Mao, Jingtong Hu, Yiran Chen, Hai Li

Proceedings of the 52nd Annual Design Automation Conference, 2015

RENO: a high-efficient reconfigurable neuromorphic computing accelerator design.

Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Hai Li, Yiran Chen, Boxun Li, Yu Wang, Hao Jiang, Mark Barnell, Qing Wu, Jianhua Joshua Yang

Proceedings of the 52nd Annual Design Automation Conference, 2015

An efficient STT-RAM-based register file in GPU architectures.

Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, Yiran Chen

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Emerging memristor technology enabled next generation cortical processor.

Hai Li, Miao Hu, Xiaoxiao Liu, Mengjie Mao, Chuandong Li, Shukai Duan

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper).

Hai Li, Xiaoxiao Liu, Mengjie Mao, Yiran Chen, Qing Wu, Mark Barnell

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A heterogeneous computing system with memristor-based neuromorphic accelerators.

Xiaoxiao Liu, Mengjie Mao, Hai Li, Yiran Chen, Hao Jiang, J. Joshua Yang, Qing Wu, Mark Barnell

Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System.

Wujie Wen, Yaojun Zhang, Mengjie Mao, Yiran Chen

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory.

Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai (Helen) Li

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Prefetching techniques for STT-RAM based last-level cache in CMP systems.

Mengjie Mao, Guangyu Sun, Yong Li, Alex K. Jones, Yiran Chen

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.

Wujie Wen, Mengjie Mao, Xiaochun Zhu, Seung H. Kang, Danghui Wang, Yiran Chen

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Unleashing the potential of MLC STT-RAM caches.

Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Coordinating prefetching and STT-RAM based last-level cache management for multicore systems.

Mengjie Mao, Hai (Helen) Li, Alex K. Jones, Yiran Chen

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Distributed replay protocol for distributed uniprocessors.

Mengjie Mao, Hong An, Bobin Deng, Tao Sun, Xuechao Wei, Wei Zhou, Wenting Han

Proceedings of the International Conference on Supercomputing, 2012

Distributed Control Independence for Composable Multi-processors.

Mengjie Mao, Hong An, Tao Sun, Qi Li, Bobin Deng, Xuechao Wei, Junrui Zhou

Proceedings of the 2012 IEEE/ACIS 11th International Conference on Computer and Information Science, Shanghai, China, May 30, 2012

Value Predicted LogSPoTM: Improve the Parallesim of Thread Level System by Using a Value Predictor.

Bobin Deng, Hong An, Qi Li, Gongming Li, Mengjie Mao

Proceedings of the 2012 IEEE/ACIS 11th International Conference on Computer and Information Science, Shanghai, China, May 30, 2012

2010

FACRA: Flexible-Core Architecture Chip Resource Abstractor.

Tao Sun, Hong An, Yongqing Ren, Mengjie Mao, Yang Liu, Mu Xu, Qi Li

Proceedings of the 2010 International Conference on Parallel and Distributed Computing, 2010