Brian Fitzgibbon

Orcid: 0000-0002-3770-5552

According to our database1, Brian Fitzgibbon authored at least 14 papers between 2009 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Spurious tones in digital delta-sigma modulators resulting from pseudorandom dither.
J. Frankl. Inst., 2015

2014
0.3-4.3 GHz Frequency-Accurate Fractional-N Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital Δ-Σ Modulator-Based Divider Controller.
IEEE J. Solid State Circuits, 2014

2013
Spurious tones in digital delta sigma modulators with pseudorandom dither.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

High speed, high accuracy fractional-N frequency synthesizer using nested mixed-radix digital Δ-Σ modulators.
Proceedings of the ESSCIRC 2013, 2013

2012
Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking - Part II: Non-Constant Input.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011
Observations Concerning the Generation of Spurious Tones in Digital Delta-Sigma Modulators Followed by a Memoryless Nonlinearity.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Spur-Free MASH DDSM With High-Order Filtered Dither.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking - Part I: Constant Input.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Calculation of Cycle Lengths in Higher Order Error Feedback Modulators With Constant Inputs.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A novel implementation of dithered digital delta-sigma modulators via bus-splitting.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Calculation of the cycle length in a HK-MASH DDSM with multilevel quantizers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Calculation of cycle lengths in higher-order MASH DDSMs with constant inputs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Calculation of cycle lengths in MASH 1-2-2 digital delta sigma modulators with a constant input.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A spur-free MASH digital delta-sigma modulator with higher order shaped dither.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009


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