Michael Peter Kennedy
Orcid: 0000-0003-3242-1056Affiliations:
- University College Cork, Ireland
According to our database1,
Michael Peter Kennedy
authored at least 159 papers
between 1991 and 2024.
Collaborative distances:
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on orcid.org
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Bibliography
2024
10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Enhanced Jitter Analysis and Minimization for Digital PLLs With Mid-Rise TDCs and its Impact on Output Phase Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
MMSE Estimator for Linearized Analysis and SNR of ADCs Tested with Sinusoidal Inputs.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Initial Condition-Dependent Spur Pattern Induced by Undithered MASH DDSM Divider Controller.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Comparison of DTC-Related Spurs in Fractional-N Digital PLLs with MASH-and-ENOP-based Divider Controllers.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Further Insights into Spur Immunity in MASH-Based Fractional-N CP-PLLs with Polynomial Nonlinearities.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Family of ΔΣ Modulators With High Spur Immunity and Low Folded Nonlinearity Noise When Used in Fractional- Frequency Synthesizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE J. Solid State Circuits, 2022
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping.
IEEE J. Solid State Circuits, 2022
A random pulse modulation approach to modeling the flicker and white noise of the charge pump of a fractional-N frequency synthesizer.
Int. J. Circuit Theory Appl., 2022
Immunity of ENOP-based Fractional-N Frequency Synthesizer to Wandering and Horn Spurs.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
Wandering Spurs in MASH-Based Fractional-N Frequency Synthesizers - How They Arise and How to Get Rid of Them
Springer, ISBN: 978-3-030-91284-0, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
MASH-Based Divider Controllers for Mitigation of Wandering Spurs in a Fractional-N Frequency Synthesizer.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
An Algorithm for Implementing a Modulator Whose Output is Spur-Free After Nonlinear Distortion.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Experimental Verification of Wandering Spur Suppression Technique in a 4.9 GHz Fractional-N Frequency Synthesizer.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
Modelling and Verification of Nonlinear Electromechanical Coupling in Micro-Scale Kinetic Electromagnetic Energy Harvesters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Influence of Initial Condition on Wandering Spur Pattern in a MASH-Based Fractional-N Frequency Synthesizer.
IEEE Trans. Circuits Syst., 2020
Analysis of Wandering Spur Patterns in a Fractional-N Frequency Synthesizer With a MASH-Based Divider Controller.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Near-Limit Kinetic Energy Harvesting From Arbitrary Acceleration Waveforms: Feasibility Study by the Example of Human Motion.
IEEE Access, 2020
A Curious Result concerning Spur Generation in MASH 1-1-1 based Fractional-N CP-PLLs with a Second-Order Nonlinearity.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
Prediction of Phase Noise and Spurs in a Nonlinear Fractional-N Frequency Synthesizer.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
4.48GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Method of Equivalent Currents for the Calculation of Magnetic Fields in Inductors and Magnets with Application to Electronics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
An Eight-Phase 40GHz RTWO in 28nm CMOS with Phase Noise Reduction Via Head and Tail Filtering.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
Observations and Analysis of Wandering Spurs in MASH-Based Fractional-N Frequency Synthesizers.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A Design Method for Nested MASH-SQ Hybrid Divider Controllers for Fractional-N Frequency Synthesizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
High-Speed Nested Cascaded MASH Digital Delta-Sigma Modulator-Based Divider Controller.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Novel Approach to Modelling Electromechanical Coupling and Testing its Self-Consistency in Micro-Scale Kinetic Electromagnetic Energy Harvesters.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
Masked Dithering of MASH Digital Delta-Sigma Modulators With Constant Inputs Using Multiple Linear Feedback Shift Registers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta-Sigma Modulators With Constant Inputs.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Nonlinearity-induced spurious tones and noise in digitally-assisted frequency synthesizers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs Using Linear Feedback Shift Registers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Comparison of analytical predictions of the noise floor due to static charge pump mismatch in fractional-n frequency synthesizers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Comparative analysis of differential colpitts and cross-coupled VCOs in 180 nm Si-Ge HBT technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Maximizing the fundamental period of a dithered digital delta-sigma modulator with constant input.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Comments on "folding of phase noise spectra in charge-pump phase-locked loops induced by frequency division".
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
On the statistical properties of phase noise in Fractional-N frequency synthesizers using successive requantizers.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
J. Frankl. Inst., 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Effective (Spur-Free) dithering of digital delta-sigma modulators with pseudorandom dither.
Proceedings of the European Conference on Circuit Theory and Design, 2015
2014
0.3-4.3 GHz Frequency-Accurate Fractional-N Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital Δ-Σ Modulator-Based Divider Controller.
IEEE J. Solid State Circuits, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2013
The Role of Charge Pump Mismatch in the Generation of Integer Boundary Spurs in Fractional-N Frequency Synthesizers: Why Worse Can Be Better.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A CMOS Injection-Locked Frequency Divider Optimized for Divide-by-Two and Divide-by-Three Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
High speed, high accuracy fractional-N frequency synthesizer using nested mixed-radix digital Δ-Σ modulators.
Proceedings of the ESSCIRC 2013, 2013
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
A high-throughput spur-free hybrid nested bus-splitting/HK-MASH digital delta-sigma modulator.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
An LC CMOS injection-locked frequency divider for divide-by-two and divide-by-three operation.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking - Part II: Non-Constant Input.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A "divide-by-odd number" direct injection CMOS LC injection-locked frequency divider.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2011
Observations Concerning the Generation of Spurious Tones in Digital Delta-Sigma Modulators Followed by a Memoryless Nonlinearity.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking - Part I: Constant Input.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Calculation of Cycle Lengths in Higher Order Error Feedback Modulators With Constant Inputs.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Observations Concerning the Locking Range in a Complementary Differential LC Injection-Locked Frequency Divider - Part II: Design Methodology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Experimental characterization of Arnold tongues in injection-locked CMOS LC frequency dividers with tail and direct injection.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Phenomenological study of an injection-locked CMOS LC frequency divider with direct injection.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
Analysis and Design of Injection-Locked Frequency Dividers by Means of a Phase-Domain Macromodel.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Prediction of the Spectrum of a Digital Delta-Sigma Modulator Followed by a Polynomial Nonlinearity.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Observations Concerning the Locking Range in a Complementary Differential LC Injection-Locked Frequency Divider - Part I: Qualitative Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A qualitative analysis of a complementary differential LC injection-locked frequency divider based on direct injection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part II: SQ-DDSM.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Calculation of cycle lengths in MASH 1-2-2 digital delta sigma modulators with a constant input.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
Design methodology for a dithered reduced complexity Digital MASH Delta-Sigma Modulator.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Design methodology for a divide-by-4 LC injection-locked frequency divider based on nonlinear analysis.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Mathematical Analysis of a Prime Modulus Quantizer MASH Digital Delta-Sigma Modulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Modeling and Simulation of Delta-Sigma Fractional-<i>N</i> PLL Frequency Synthesizer in Verilog-AMS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Hard-Fault Detection and Diagnosis During the Application of Model-Based Data Converter Testing.
J. Electron. Test., 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Optimizing the design of an injection-locked frequency divider by means of nonlinear analysis.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
Test Development Through Defect and Test Escape Level Estimation for Data Converters.
J. Electron. Test., 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
The optimum power conversion efficiency and associated gain of an LC CMOS oscillator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Use of the Step Invariant Transform to Design a 2nd Order Continuous Time Complex Sigma-Delta ADC.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
IEEE Trans. Circuits Syst. II Express Briefs, 2005
Int. J. Bifurc. Chaos, 2005
Overcoming Test Setup Limitations by Applying Model-Based Testing to High-Precision ADCs.
J. Electron. Test., 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Comments on the effectiveness of the Szabo and Kolumban solution to false lock in sampling PLL frequency synthesizer.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Accurate modeling and experimental validation of an injection-locked frequency divider.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
The Devil's Staircase as a method of comparing injection-locked frequency divider topologies.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
A fast and simple implementation of Chua's oscillator using a "cubic-like" Chua diode.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Observations on the relationship between energy transfer efficiency and phase noise in an LC oscillator.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
A general method to predict the amplitude of oscillation in nearly sinusoidal oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Comput. Stand. Interfaces, 2004
A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillators.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
Int. J. Bifurc. Chaos, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 2003 Design, 2003
2002
Proc. IEEE, 2002
Int. J. Bifurc. Chaos, 2002
Int. J. Bifurc. Chaos, 2002
Implementation of Model-Based Testing for Medium to High-Resolution Nyquist-Rate ADCs.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
2001
Process Deviations and Spot Defects: Two Aspects of Test and Test Development for Mixed-Signal Circuits.
J. Electron. Test., 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
J. Frankl. Inst., 2000
Int. J. Circuit Theory Appl., 2000
Int. J. Bifurc. Chaos, 2000
Int. J. Bifurc. Chaos, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 Design, 2000
1999
IEEE Trans. Instrum. Meas., 1999
J. Circuits Syst. Comput., 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Simulation of the multipath performance of FM-DCSK digital communications using chaos.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Ultra-fast simulator developed in Matlab environment to evaluate multipath performance of FM-DCSK RF system.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
1993
J. Circuits Syst. Comput., 1993
Synthesis of continuous three-segment voltage-controlled piecewise-linear resistors for Chua's circuit family using operational amplifiers, diodes and linear resistors.
Int. J. Circuit Theory Appl., 1993
Proceedings of the Chua's Circuit: A Paradigm for Chaos, 1993
Proceedings of the Chua's Circuit: A Paradigm for Chaos, 1993
1991
Int. J. Circuit Theory Appl., 1991