Brian Lee

Affiliations:

ChangXin Memory Technologies, Inc. (CXMT), Design Center, Hefei, China

According to our database¹, Brian Lee authored at least 6 papers between 2021 and 2023.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

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Bibliography

2023

Pseudo differential DQS receiver for eliminating channel Hi-z noise.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

A low power consumption and higher performance DDR5 receiver based on a direct feedback DFE and dedicated reference voltage for 1<sup>st</sup> TAP DFE.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Fast-Lock DLL with Prediction-Based Fast-Track FDL Structure for DDR5 SDRAMs.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2021

Adaptive DLL Update Scheme for Power Fluctuation Immunity Using Phase Error Detector.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

A 2-stage with 3-stack 1-tap DFE Sense Amplifier based on Dual Reference for High Speed & Low Power DRAM Interface.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Adaptive OCD and ODT Control for Channel S/I Enhancement in DDR4 SDRAM.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Brian Lee

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