Kanyu Cao

According to our database¹, Kanyu Cao authored at least 9 papers between 2019 and 2023.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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Bibliography

2023

Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2023

Dielectric Relaxation Performance of DRAM Storage Capacitors and Ways of Improvement.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Memory Workshop, 2023

2021

Pitch Device Design in 10nm-Class DRAM Process through DTCO.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Impact of Hydrogen Anneal on Peripheral PMOS NBTI and Array Transistor GIDL in DRAM.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Adaptive DLL Update Scheme for Power Fluctuation Immunity Using Phase Error Detector.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

A 2-stage with 3-stack 1-tap DFE Sense Amplifier based on Dual Reference for High Speed & Low Power DRAM Interface.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Adaptive OCD and ODT Control for Channel S/I Enhancement in DDR4 SDRAM.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2019

Improved Model for ESD Failure Caused by Stressing No Connect Pin.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Improve DRAM Leakage Issue During RAS Operational Phase Through TCAD Simulation.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Kanyu Cao

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