Burhan Khurshid

According to our database, Burhan Khurshid authored at least 10 papers between 2014 and 2021.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2021

An Efficient Fixed-Point Multiplier Based on CORDIC Algorithm.

Burhan Khurshid, Javeed Jeelani Khan

J. Circuits Syst. Comput., 2021

2018

Improved Synthesis of Generalized Parallel Counters on FPGAs Using Only LUTs.

Burhan Khurshid

J. Circuits Syst. Comput., 2018

2017

Technology-Optimized Fixed-Point Bit-Parallel Multipliers for FPGAs.

Burhan Khurshid

J. Signal Process. Syst., 2017

Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAs.

Burhan Khurshid, Roohie Naaz Mir

J. Circuits Syst. Comput., 2017

LUT based realization of fixed-point multipliers targeting state-of-art FPGAs.

Burhan Khurshid

Des. Autom. Embed. Syst., 2017

An Efficient FIR Filter Structure Based on Technology-Optimized Multiply-Adder Unit Targeting LUT-Based FPGAs.

Burhan Khurshid, Roohie Naaz Mir

Circuits Syst. Signal Process., 2017

2016

Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs.

Burhan Khurshid, Roohie Naaz Mir

Int. J. High Perform. Syst. Archit., 2016

2015

High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs.

Burhan Khurshid, Roohie Naaz Mir

Int. J. Reconfigurable Comput., 2015

High Efficiency Generalized Parallel Counters for Xilinx FPGAs.

Burhan Khurshid, Roohie Naaz Mir

Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015

2014

A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA Platforms.

Burhan Khurshid, Roohie Naaz Mir

Proceedings of the 2014 27th International Conference on VLSI Design, 2014