Câncio Monteiro

Sensors, 2021

2018

Low Power Source Biased Semi-Adiabatic Logic Circuit for IoT Devices.

[BibT_eX]

[DOI]

Apolinario Maria

Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018

2015

Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2015

2014

Process variation verification of low-power secure CSSAL AES S-box circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

An LSI implementation of a bit-parallel cellular multiplier over GF(2<sup>4</sup>) using secure charge-sharing symmetric adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level.

[BibT_eX]

[DOI]

Microelectron. J., 2013

Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks.

[BibT_eX]

[DOI]

Proceedings of the 36th International Conference on Telecommunications and Signal Processing, 2013

DPA resistance of charge-sharing symmetric adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Low power secure CSSAL bit-parallel multiplier over GF(2<sup>4</sup>) in 0.18μm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2011

Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card.

[BibT_eX]

[DOI]