Caroline Lelandais-Perrault

According to our database1, Caroline Lelandais-Perrault authored at least 22 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Design of an ECG front-end considering ST segment distortion.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

2020
A CMOS readout circuit for a low shunt resistance IR photo-detector.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Pixel circuit design for an accumulation mode BDJ APS in a 0.18µm CMOS technology.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Impacts of Crest Factor Reduction and Digital Predistortion on Linearity and Power Efficiency of Power Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A new algorithm for an incremental sigma-delta converter reconstruction filter.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

Optimization of a pruned 2-D Digital Predistortion Model Structure for Power Amplifiers Linearization.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

2018
A -40 to 250°C Triple Modular Redundancy Temperature Sensor for Turbofan Engines.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

2017
A 14-b two-step inverter-based ΣΔ ADC for CMOS image sensor.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Analog bandwidth mismatch compensation for time-interleaved ADCs using FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A new two-step ΣΔ architecture column-parallel ADC for CMOS image sensor.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

2014
Mismatch calibration methods for high-speed time-interleaved ADCs.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
SNR efficient approach for the design of Hybrid Filter Bank A/D converters.
Proceedings of the IEEE International Conference on Acoustics, 2013

2012
Robustness of parallel multi-rate A/D converters to anti-aliasing filter non-idealities.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011
Optimization of bandpass charge sampling filters in hybrid filter banks converters for cognitive radio applications.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Synthesis of Subband Hybrid Filter Banks ADCs with finite word-length coefficients using adaptive equalization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Wideband, Bandpass, and Versatile Hybrid Filter Bank A/D Conversion for Software Radio.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Synthesis of complex subband Hybrid Filter Banks A/D converters using adaptive filters.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Adaptive equalization for calibration of subband hybrid filter banks A/D converters.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2005
Band-pass hybrid filter bank A/D converters with software-controlled bandwidth and resolution.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
Synthesis of hybrid filter banks for A/D conversion with implementation constraints - mixed distortion/aliasing optimization $.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
A parallel structure of a continuous-time filter for band-pass sigma-delta A/D converters.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003


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