Pascal Urard

According to our database1, Pascal Urard authored at least 38 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
Artificial neural network-based solution for PSP MOSFET model card extraction.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
Reinforcement Learning for Analog Sizing Optimization.
Proceedings of the 19th International Conference on Synthesis, 2023

Performance Modeling and Estimation of a Configurable Output Stationary Neural Network Accelerator.
Proceedings of the 35th IEEE International Symposium on Computer Architecture and High Performance Computing, 2023

Quantization Modes for Neural Network Inference: ASIC Implementation Trade-offs.
Proceedings of the International Joint Conference on Neural Networks, 2023

2022
40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

2020
Software Controlled Low Cost Thermoelectric Energy Harvester for Ultra-Low Power Wireless Sensor Nodes.
IEEE Access, 2020

2015
GreenNet: An Energy-Harvesting IP-Enabled Wireless Sensor Network.
IEEE Internet Things J., 2015

A self-powered IPv6 bidirectional wireless sensor & actuator network for indoor conditions.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A Nano quiescent Current Power Management for Autonomous Wireless Sensor Network.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
Internet-of-energy: combining embedded computing and communication for the smart grid.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Wireless sensor systems: Solution & technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
Low-complexity decoding for non-binary LDPC codes in high order fields.
IEEE Trans. Commun., 2010

A 1 GHz Digital Channel Multiplexer for Satellite Outdoor Unit.
IEEE J. Solid State Circuits, 2010

Silicon 3D-integration technology and systems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Static Address Generation Easing: a design methodology for parallel interleaver architectures.
Proceedings of the IEEE International Conference on Acoustics, 2010

A new approach for minimizing buffer capacities with throughput constraint for embedded system design.
Proceedings of the 8th ACS/IEEE International Conference on Computer Systems and Applications, 2010

2009
Functional Equivalence Verification Tools in High-Level Synthesis Flows.
IEEE Des. Test Comput., 2009

A 1GHz digital channel multiplexer for satellite OutDoor Unit based on a 65nm CMOS transceiver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling Satellite-Transmission Portable Devices.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Split non-binary LDPC codes.
Proceedings of the 2008 IEEE International Symposium on Information Theory, 2008

Leveraging sequential equivalence checking to enable system-level to RTL flows.
Proceedings of the 45th Design Automation Conference, 2008

A thresholding algorithm for improved Split-Row decoding of LDPC codes.
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

2007
Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels
CoRR, 2007

A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A design flow dedicated to multi-mode architectures for DSP applications.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Low-Complexity, Low-Memory EMS Algorithm for Non-Binary LDPC Codes.
Proceedings of IEEE International Conference on Communications, 2007

A design methodology for space-time adapter.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Application of a design space exploration tool to enhance interleaver generation.
Proceedings of the 15th European Signal Processing Conference, 2007

2006
Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems.
EURASIP J. Adv. Signal Process., 2006

Building a standard ESL design and verification methodology: is it just a dream?
Proceedings of the 43rd Design Automation Conference, 2006

2005
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3).
Proceedings of the 42nd Design Automation Conference, 2005

ESL: building the bridge between systems to silicon.
Proceedings of the 42nd Design Automation Conference, 2005

IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003
An Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003


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