Chae-Hyeon Lim

According to our database¹, Chae-Hyeon Lim authored at least 2 papers in 2025.

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2025

SystemVerilog-Based Modeling and Verification of 40-Gb/s/Lane PAM-3 Transmitter for USB4.0 Gen4.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Synthesis, 2025

SystemVerilog-Based Modeling and Verification of 25.6-GBaud/Lane PAM-3 Receiver.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Synthesis, 2025