Yong-Gyu Yu

According to our database, Yong-Gyu Yu authored at least 4 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A 0.067-pJ/bit/dB Transmitter for Low-Power Memory Interfaces With Charge-Pump-Aided On-Demand Sub-Pre-Emphasis for Worst-Case Pattern Compensation.

Jongchan Lee, Yong-Gyu Yu, Jong-Min Lee, Joo-Hyung Chae

IEEE Trans. Circuits Syst. II Express Briefs, June, 2026

2025

SystemVerilog-Based Modeling and Verification of 40-Gb/s/Lane PAM-3 Transmitter for USB4.0 Gen4.

Yong-Gyu Yu, Ju-Hyeong Yun, Chae-Hyeon Lim, Joo-Hyung Chae

Proceedings of the 21st International Conference on Synthesis, 2025

SystemVerilog-Based Modeling and Verification of 25.6-GBaud/Lane PAM-3 Receiver.

Chae-Hyeon Lim, Ju-Hyeong Yun, Yong-Gyu Yu, Joo-Hyung Chae

Proceedings of the 21st International Conference on Synthesis, 2025

A 1.05-V/0.5-V 15.6-Gb/s NRZ Transmitter Achieving 0.76-pJ/bit Energy Efficiency for Low-Power Memory Interfaces.

Ju-Hyeong Yun, Yong-Gyu Yu, Jongchan Lee, Joo-Hyung Chae

Proceedings of the International Conference on Electronics, Information, and Communication, 2025