Joo-Hyung Chae
Orcid: 0000-0001-6354-5612
According to our database1,
Joo-Hyung Chae
authored at least 33 papers
between 2013 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 1-Kb 6T 1C XNOR-DRAM Compute-In-Memory Macro With Signed Bit Adder Block for CNN Operations.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
2023
Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces.
IEEE J. Solid State Circuits, September, 2023
Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM Measurement.
IEEE Trans. Instrum. Meas., 2023
A 50-1600 MHz Wide-Range Digital Duty-Cycle Corrector With Counter-Based Half-Cycle Delay Line.
IEEE Access, 2023
Module Implementation and Simulation of Timing Constraint Check Function of I2C Protocol Using Verilog.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
2022
A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.
IEEE J. Solid State Circuits, 2022
Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters.
IEEE Access, 2022
2021
A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer.
IEEE J. Solid State Circuits, 2021
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface.
IEEE J. Solid State Circuits, 2021
A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface.
IEEE Access, 2021
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
2019
A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface.
IEEE J. Solid State Circuits, 2018
A 3.2 Gb/s 16-Channel Transmitter for Intra-Panel Interfaces, With Independently Controllable Output Swing, Common-Mode Voltage, and Equalization.
IEEE Access, 2018
Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
2017
An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface.
Proceedings of the International SoC Design Conference, 2017
A 0.13pJ/bit, referenceless transceiver with clock edge modulation for a wired intra-BAN communication.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2015
A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2013
High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line.
Proceedings of the ESSCIRC 2013, 2013