Chaitali Sathe

According to our database, Chaitali Sathe authored at least 5 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

From High-Level Synthesis Lite to High-Level Synthesis Full: Unlocking HLS tool Limitations.

Benjamin Carrion Schafer, Chaitali Sathe

ACM Trans. Design Autom. Electr. Syst., March, 2026

2025

Efficient and Secure Cloud-based Split Logic Synthesis.

Chaitali Sathe, Yiorgos Makris, Benjamin Carrión Schäfer

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

Circumventing Restrictions in Commercial High-Level Synthesis Tools.

Benjamin Carrion Schafer, Chaitali G. Sathe

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

MANTIS: Machine Learning-Based Approximate ModeliNg of RedacTed Integrated CircuitS.

Chaitali Sathe, Yiorgos Makris, Benjamin Carrion Schafer

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Predictive Model Attack for Embedded FPGA Logic Locking.

Prattay Chowdhury, Chaitali Sathe, Benjamin Carrión Schäfer

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022