Chaitali Sathe

Orcid: 0009-0003-2719-7237

According to our database1, Chaitali Sathe authored at least 5 papers between 2022 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
From High-Level Synthesis Lite to High-Level Synthesis Full: Unlocking HLS tool Limitations.
ACM Trans. Design Autom. Electr. Syst., March, 2026

2025
Efficient and Secure Cloud-based Split Logic Synthesis.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
Circumventing Restrictions in Commercial High-Level Synthesis Tools.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
MANTIS: Machine Learning-Based Approximate ModeliNg of RedacTed Integrated CircuitS.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Predictive Model Attack for Embedded FPGA Logic Locking.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022


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