Chandrashekhar
According to our database1,
Chandrashekhar
authored at least 2 papers
between 2008 and 2024.
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Bibliography
2024
Proceedings of the 15th International Conference on Computing Communication and Networking Technologies, 2024
2008
An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008