Chandrashekhar

According to our database1, Chandrashekhar authored at least 1 paper in 2008.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of six.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2008
An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008


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