Chao-Hung Lu

According to our database, Chao-Hung Lu authored at least 7 papers between 2007 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs.

Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih

Integr., 2013

2011

Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits.

Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu

J. Inf. Sci. Eng., 2011

2009

Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design.

Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Effective decap insertion in area-array SoC floorplan design.

Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu

ACM Trans. Design Autom. Electr. Syst., 2008

An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning.

Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu

J. Inf. Sci. Eng., 2008

2007

Using power gating techniques in area-array SoC floorplan design.

Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu

Proceedings of the 2007 IEEE International SOC Conference, 2007

On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design.

Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007