Chien-Nan Jimmy Liu
Orcid: 0000-0002-4907-898X
According to our database1,
Chien-Nan Jimmy Liu
authored at least 96 papers
between 1999 and 2023.
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Bibliography
2023
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization.
ACM Trans. Design Autom. Electr. Syst., March, 2023
Proceedings of the 19th International Conference on Synthesis, 2023
Proceedings of the 2023 International Symposium on Physical Design, 2023
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
Proceedings of the 18th International Conference on Synthesis, 2022
Behavioral Level Simulation Framework to Support Error-Aware CNN Training with In-Memory Computing.
Proceedings of the 18th International Conference on Synthesis, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
ACM Trans. Design Autom. Electr. Syst., 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2019
Proceedings of the 16th International Conference on Synthesis, 2019
Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines.
Proceedings of the International Conference on Computer-Aided Design, 2019
2018
Spec-to-Layout Automation Flow for Buck Converters with Current-Mode Control in SOC Applications.
Proceedings of the 15th International Conference on Synthesis, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
An Incremental Simulation Technique Based on Delta Model for Lifetime Yield Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Non-regression approach for the behavioral model generator in mixed-signal system verification.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
Proceedings of the 26th IEEE Asian Test Symposium, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the VLSI Design, Automation and Test, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Simultaneous optimization for low dropout regulator and its error amplifier with process variation.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs.
Integr., 2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
ACM Trans. Design Autom. Electr. Syst., 2012
Levelized High-Level Current Model of Logic Blocks for Dynamic Supply Noise Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012
2011
Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits.
J. Inf. Sci. Eng., 2011
IEEE Des. Test Comput., 2011
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Measurement and Evaluation of the Bioelectrical Impedance of the Human Body by Deconvolution of a Square Wave.
IEICE Trans. Inf. Syst., 2010
Measuring the Transmission Characteristic of the Human Body in an Electrostatic-Coupling Intra Body Communication System Using a Square Test Stimulus.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Automatic circuit adjustment technique for process sensitivity reduction and yield improvement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 47th Design Automation Conference, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System.
IEICE Trans. Commun., 2009
IEICE Trans. Electron., 2009
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design.
Proceedings of the Design, Automation and Test in Europe, 2009
A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
ACM Trans. Design Autom. Electr. Syst., 2008
Long-Range Prediction for Real-Time MPEG Video Traffic: An H<sub>infty</sub> Filter Approach.
IEEE Trans. Circuits Syst. Video Technol., 2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning.
J. Inf. Sci. Eng., 2008
Quick supply current waveform estimation at gate level using existed cell library information.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
J. Inf. Sci. Eng., 2007
An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
IEEE Des. Test Comput., 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEICE Trans. Electron., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the IEEE International Conference on Systems, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A novel approach for high-level power modeling of sequential circuits using recurrent neural networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
IEEE Des. Test Comput., 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of ASP-DAC 2001, 2001
2000
IEEE Des. Test Comput., 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the IEEE International Conference On Computer Design, 1999