Chao-Shiun Wang

According to our database1, Chao-Shiun Wang authored at least 9 papers between 2005 and 2012.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2012
A 4.9-mW 4-Gb/s single-to-differential TIA with current-amplifying regulated cascode.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011
A 90 nm CMOS V-Band Low-Noise Active Balun With Broadband Phase-Correction Technique.
IEEE J. Solid State Circuits, 2011

A low power W-band PLL with 17-mW in 65-nm CMOS technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A low power high reliability dual-path noise-cancelling LNA for WSN applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A 77 GHz power amplifier using transformer-based power combiner in 90 nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A 60-GHz Phased Array Receiver Front-End in 0.13-mu hboxm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008
A low power 20 GHz 1.5 Gb/s CMOS injection-pulling FSK modulator and frequency discriminator for 60GHz links.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 0.13μm CMOS fully differential receiver with on-chip baluns for 60GHz broadband wireless communications.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2005
A multi-band multi-standard RF front-end IEEE 802.16a for IEEE 802.16a and IEEE 802.11 a/b/g applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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