Chorng-Kuang Wang
According to our database1,
Chorng-Kuang Wang
authored at least 35 papers
between 1996 and 2014.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2008, "For contributions to communications circuit design and for leadership in promoting the profession".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2014
A 1V 10-bit 500KS/s energy-efficient SAR ADC using Master-Slave DAC technique in 180nm CMOS.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
2013
A CMOS Cantilever-Based Label-Free DNA SoC With Improved Sensitivity for Hepatitis B Virus Detection.
IEEE Trans. Biomed. Circuits Syst., 2013
2012
A fully integrated hepatitis B virus DNA detection SoC based on monolithic polysilicon nanowire CMOS process.
Proceedings of the Symposium on VLSI Circuits, 2012
A 4.9-mW 4-Gb/s single-to-differential TIA with current-amplifying regulated cascode.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the 12th International Conference on ITS Telecommunications, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A 90 nm CMOS V-Band Low-Noise Active Balun With Broadband Phase-Correction Technique.
IEEE J. Solid State Circuits, 2011
An 85-GHz injection-locked frequency divider with current-reuse pre-amplifier technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
Joint Carrier Synchronization and Equalization Algorithm for Packet-Based OFDM Systems Over the Multipath Fading Channel.
IEEE Trans. Veh. Technol., 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Design and analysis of cost-efficient IFFT/FFT processor chip for wireless OFDM systems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Joint Carrier Synchronization and Equalizaiton Algorithm for OFDM Systems - Loop-Delay Analysis and Complexity Consideration.
Proceedings of the 70th IEEE Vehicular Technology Conference, 2009
Joint Carrier Synchronization and Equalization Algorithm for OFDM Systems - Closed-Loop Derivation.
Proceedings of the 69th IEEE Vehicular Technology Conference, 2009
Cost-Effective Equalization for STBC MIMO/MISO OFDM Systems over Multipath Fading Channel.
Proceedings of the 70th IEEE Vehicular Technology Conference, 2009
A MIMO-OFDM digital baseband receiver design with adaptive equalization technique for IEEE 802.16 WMAN.
Proceedings of the IEEE International Conference on Acoustics, 2009
2008
Joint Carrier Synchronization and Equalization for OFDM Systems Over Multipath Fading Channel.
Proceedings of the 68th IEEE Vehicular Technology Conference, 2008
A low power 20 GHz 1.5 Gb/s CMOS injection-pulling FSK modulator and frequency discriminator for 60GHz links.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
A 0.13μm CMOS fully differential receiver with on-chip baluns for 60GHz broadband wireless communications.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
A CMOS RF front-end with on-chip antenna for V-band broadband wireless communications.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2005
A multi-band multi-standard RF front-end IEEE 802.16a for IEEE 802.16a and IEEE 802.11 a/b/g applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 13th European Signal Processing Conference, 2005
2004
A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2001
A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifier.
IEEE J. Solid State Circuits, 2001
A wide pull-in range fast acquisition hardware-sharing two-fold carrier recovery loop.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
1999
A 2-V 7.2° jitter AM-suppression CMOS amplifier using current-mode hybrid magnitude control.
IEEE J. Solid State Circuits, 1999
1996