Chetan D. Parikh

According to our database, Chetan D. Parikh authored at least 15 papers between 2008 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Deterministic Digital Calibration Technique for 1.5 bits/stage Pipelined and Algorithmic ADCs with Finite op-amp Gain and Large Capacitance Mismatches.

Chinmaye Ramamurthy, Chetan D. Parikh, Subhajit Sen

Circuits Syst. Signal Process., 2021

Deterministic Digital Calibration of 1.5 bits/stage Pipelined ADCs by Direct Extraction of Calibration Coefficients.

Chinmaye Ramamurthy, Chetan D. Parikh, Subhajit Sen

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Digital Calibration of 1.5 bits/stage Algorithmic ADC.

Chinmaye Ramamurthy, Chetan D. Parikh, Subhajit Sen

Proceedings of the 18th International SoC Design Conference, 2021

2020

High Performance Operational Amplifier with 90dB Gain in SCL 180nm Technology.

Surya Padma, Sounak Das, Subhajit Sen, Chetan D. Parikh

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019

Wake-up circuit for PAM4 receiver.

Vamsi Krishna Guduru, Richa Gupta, Bhavani Lakshmi Polareddy, M. Anish Unnikrishnan, Chetan D. Parikh, Subhajit Sen

Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019

2018

A Systematic Approach to Determining the Weights of the Capacitors in the DAC of a Non-binary Redundant SAR ADCs.

Uma Mukund Kulkarni, Chetan D. Parikh, Subhajit Sen

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017

A Calibration Technique for Current Steering DACs - Self Calibration with Capacitor Storage.

Pallavi G. Darji, Chetan D. Parikh

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2016

Novel Analog Calibration Technique for Current-Steering DACs' Dynamic Performance.

Pallavi G. Darji, Chetan D. Parikh

Circuits Syst. Signal Process., 2016

New technique to improve transient response of LDO regulators without an off-chip capacitor.

Chetan D. Parikh, Gopal Agarwal

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015

A low power low area capacitor array based Digital to Analog Converter architecture.

A. Purushothaman, Chetan D. Parikh

Microelectron. J., 2015

A New Delay Model and Geometric Programming-Based Design Automation for Latched Comparators.

A. Purushothaman, Chetan D. Parikh

Circuits Syst. Signal Process., 2015

Novel Analog Calibration Technique for Current-Steering DACs.

Pallavi G. Darji, Chetan D. Parikh

Circuits Syst. Signal Process., 2015

2013

A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain Amplifier.

Vivek Verma, Chetan D. Parikh

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

10 Gbps Current Mode Logic I/O Buffer.

Akhil Rathore, Chetan D. Parikh

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

2008

Low power high bandwidth amplifier with RC Miller and gain enhanced feedforward compensation.

Shagun Bajoria, Vineet Kumar Singh, Raju Kunde, Chetan D. Parikh

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008