Chia-Pin R. Liu

According to our database, Chia-Pin R. Liu authored at least 7 papers between 1999 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2009

A Novel Floorplanning for Hierarchical VLSI Design.

Chia-Pin R. Liu

Proceedings of the ISCA 24th International Conference on Computers and Their Applications, 2009

Floorplan Optimization for Hierarchical VLSI Design.

Chia-Pin R. Liu

Proceedings of the ISCA 22nd International Conference on Computer Applications in Industry and Engineering, 2009

2008

A Novel Synthesis for Dynamic CMOS Circuits.

Chia-Pin R. Liu

Proceedings of the ISCA 21st International Conference on Computer Applications in Industry and Engineering, 2008

2007

Gate Model Extraction from CMOS Transistor Circuits.

Chia-Pin R. Liu

Proceedings of the ISCA 20th International Conference on Computer Applications in Industry and Engineering, 2007

2006

Traffic Monitoring for a Network Visualization Environment.

Chia-Pin R. Liu, Shaofeng Yang, Mahmound A. Manzoul

Proceedings of the 21st International Conference on Computers and Their Applications, 2006

Transistor-mapped binary decision diagram for CMOS circuits.

Chia-Pin R. Liu

Proceedings of the ISCA 19th International Conference on Computer Applications in Industry and Engineering, 2006

1999

Transistor Level Synthesis for Static CMOS Combinational Circuits.

Chia-Pin R. Liu, Jacob A. Abraham

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999