Jacob A. Abraham

According to our database1, Jacob A. Abraham authored at least 424 papers between 1974 and 2019.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2001, "For outstanding contributions in the fields of fault tolerant computing, automatic test generation and design for test, and formal verification.".

Timeline

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Bibliography

2019
Spectral Leakage-Driven Loopback Scheme for Prediction of Mixed-Signal Circuit Specifications.
IEEE Trans. Industrial Electronics, 2019

A Broadband CMOS RF Front End for Direct Sampling Satellite Receivers.
J. Solid-State Circuits, 2019

Resiliency Demands on Next Generation Critical Embedded Systems.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Cross-Layer Resilience: Challenges, Insights, and the Road Ahead.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

ESIFT: Efficient System for Error Injection.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Cross-Layer Control Adaptation for Autonomous System Resilience.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Effective Control Flow Integrity Checks for Intrusion Detection.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

2017
A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS.
IEEE Trans. on Circuits and Systems, 2017

Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
CoRR, 2017

Automatic Assertion Generation for Simulation, Formal Verification and Emulation.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Power prediction of embedded scalar and vector processor: Challenges and solutions.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Design of efficient error resilience in signal processing and control systems: From algorithms to circuits.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS.
IEEE Trans. VLSI Syst., 2016

CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores.
CoRR, 2016

Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Design of Self Calibrating and Error Resilient Mixed-Signal Systems for Signal Processing, Communications and Control.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Single Trojan injection model generation and detection.
Proceedings of the 17th Latin-American Test Symposium, 2016

Checksum based error detection in linearized representations of non linear control systems.
Proceedings of the 17th Latin-American Test Symposium, 2016

Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states.
Proceedings of the 2016 IEEE International Test Conference, 2016

Cross-layer resilience: are high-level techniques always better?
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Clear: c̲ross-l̲ayer e̲xploration for a̲rchitecting r̲esilience combining hardware and software techniques to tolerate soft errors in processor cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Quality Aware Error Detection in 2-D Separable Linear Transformation.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Delay Defect Diagnosis Methodology Using Path Delay Measurements.
IEICE Transactions, 2015

Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction.
J. Electronic Testing, 2015

In-depth soft error vulnerability analysis using synthetic benchmarks.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Tutorial T3: Error Resilient Real-Time Embedded Systems: Computing, Communications and Control.
Proceedings of the 28th International Conference on VLSI Design, 2015

The future of fault tolerant computing.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Power-aware multi-voltage custom memory models for enhancing RTL and low power verification.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Formal Verification ATPG Search Engine Emulator (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Efficient soft error vulnerability estimation of complex designs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Bitstream-Driven Built-In Characterization for Analog and Mixed-Signal Embedded Circuits.
IEEE Trans. on Circuits and Systems, 2014

Dynamic Performance Characterization of Embedded Single-Ended Mixed-Signal Circuits.
IEEE Trans. on Circuits and Systems, 2014

Addressing failures in exascale computing.
IJHPCA, 2014

Fast evaluation of test vector sets using a simulation-based statistical metric.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players?
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Harmonic distortion correction for 8-bit delay line ADC using gray code.
Proceedings of the 15th Latin American Test Workshop, 2014

EAGLE: A regression model for fault coverage estimation using a simulation based metric.
Proceedings of the 2014 International Test Conference, 2014

A novel algorithm for sparse FFT pruning and its applications to OFDMA technology.
Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014

Connecting different worlds - Technology abstraction for reliability-aware design and Test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A novel low power 11-bit hybrid ADC using flash and delay line architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Error Resilient Real-Time State Variable Systems for Signal Processing and Control.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Rethinking error injection for effective resilience.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories.
IEEE Trans. VLSI Syst., 2013

Concurrent Path Selection Algorithm in Statistical Timing Analysis.
IEEE Trans. VLSI Syst., 2013

Asynchronous Measurement of Transient Phase-Shift Resulting From RF Receiver State-Change.
IEEE Trans. on Circuits and Systems, 2013

Capacitor-Coupled Built-Off Self-Test in Analog and Mixed-Signal Embedded Systems.
IEEE Trans. on Circuits and Systems, 2013

Special session 12B: Panel post-silicon validation & test in huge variance era.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Enhanced algorithm of combining trace and scan signals in post-silicon validation.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

A framework for low overhead hardware based runtime control flow error detection and recovery.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Dynamic Trace Signal Selection for Post-Silicon Validation.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faults.
Proceedings of the 2013 IEEE International Test Conference, 2013

On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Real-time checking of linear control systems using analog checksums.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor.
Proceedings of the Design, Automation and Test in Europe, 2013

Quantitative evaluation of soft error injection techniques for robust system design.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Digital Calibration for 8-Bit Delay Line ADC Using Harmonic Distortion Correction.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Phase-Aware Multitone Digital Signal Based Test for RF Receivers.
IEEE Trans. on Circuits and Systems, 2012

Imbalance-Based Self-Test for High-Speed Mixed-Signal Embedded Systems.
IEEE Trans. on Circuits and Systems, 2012

Testability-Driven Statistical Path Selection.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

On Computing Criticality in Refactored Timing Graphs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

A reduced voltage swing circuit using a single supply to enable lower voltage operation for SRAM-based memory.
Microelectronics Journal, 2012

Automatic and Correct Register Transfer Level Annotations for Low Power Microprocessor Design.
J. Low Power Electronics, 2012

A Novel fractional-n PLL Based on a Simple Reference Multiplier.
Journal of Circuits, Systems, and Computers, 2012

Built-in Self Test of RF Subsystems with Integrated Detectors.
J. Electronic Testing, 2012

A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement.
J. Electronic Testing, 2012

Calibration Enabled Scalable Current Sensor Module for Quiescent Current Testing.
J. Electronic Testing, 2012

An aging-aware flip-flop design based on accurate, run-time failure prediction.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

A Built-In Self-Test scheme for DDR memory output timing test and measurement.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

An oscillation-based test structure for timing information extraction.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Test of phase interpolators in high speed I/Os using a sliding window search.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management.
Proceedings of the 25th International Conference on VLSI Design, 2012

FALCON: Rapid statistical fault coverage estimation for complex designs.
Proceedings of the 2012 IEEE International Test Conference, 2012

Stream cipher hash based execution monitoring (SCHEM) framework for intrusion detection on embedded processors.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Functional test generation for hard to detect stuck-at faults using RTL model checking.
Proceedings of the 17th IEEE European Test Symposium, 2012

Indirect method for random jitter measurement on SoCs using critical path characterization.
Proceedings of the 17th IEEE European Test Symposium, 2012

On-chip source synchronous interface timing test scheme with calibration.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Transformer-Coupled Loopback Test for Differential Mixed-Signal Dynamic Specifications.
IEEE Trans. Instrumentation and Measurement, 2011

Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits.
IEEE Trans. on Circuits and Systems, 2011

CEDA: Control-Flow Error Detection Using Assertions.
IEEE Trans. Computers, 2011

Pseudorandom Test of Nonlinear Analog and Mixed-Signal Circuits Based on a Volterra Series Model.
J. Electronic Testing, 2011

Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip.
J. Electronic Testing, 2011

Efficient and product-representative timing model validation.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Tutorial: "Manufacturing test of systems-on-a-chip (SoCs)".
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Testability driven statistical path selection.
Proceedings of the 48th Design Automation Conference, 2011

On-Chip Programmable Dual-Capture for Double Data Rate Interface Timing Test.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Post-Silicon Timing Validation Method Using Path Delay Measurements.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Robust power gating reactivation by dynamic wakeup sequence throttling.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

System accuracy estimation of SRAM-based device authentication.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Path criticality computation in parameterized statistical timing analysis.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits.
J. Electronic Testing, 2010

On-Chip Delay Measurement Based Response Analysis for Timing Characterization.
J. Electronic Testing, 2010

Multitone digital signal based test for RF receivers.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Estimation of maximum application-level power supply noise.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

High speed recursion-free CORDIC architecture.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPM.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

An improved SOM-based visualization technique for DNA microarray data analysis.
Proceedings of the International Joint Conference on Neural Networks, 2010

Toward reliable SRAM-based device identification.
Proceedings of the 28th International Conference on Computer Design, 2010

A delay measurement method using a shrinking clock signal.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control.
Proceedings of the 15th European Test Symposium, 2010

Calibration-enabled scalable built-in current sensor compatible with very low cost ATE.
Proceedings of the 15th European Test Symposium, 2010

At-speed Test of High-Speed DUT Using Built-Off Test Interface.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

A novel characterization technique for high speed I/O mixed signal circuit components using random jitter injection.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level.
J. Low Power Electronics, 2009

Critical Path Selection for Delay Testing Considering Coupling Noise.
J. Electronic Testing, 2009

On-Line Calibration and Power Optimization of RF Systems Using a Built-In Detector.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Recursive Path Selection for Delay Fault Testing.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Characterization of sequential cells for constraint sensitivities.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Functionally valid gate-level peak power estimation for processors.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

An Area Efficient On-chip Static IR Drop Detector/Evaluator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Hybrid BiST Solution for Analog to Digital Converters with Low-cost Automatic Test Equipment Compatibility.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Error detection in 2-D Discrete Wavelet lifting transforms.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

A high throughput FFT processor with no multipliers.
Proceedings of the 27th International Conference on Computer Design, 2009

A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip.
Proceedings of the 14th IEEE European Test Symposium, 2009

SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

A Random Jitter RMS Estimation Technique for BIST Applications.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Small-delay defect detection in the presence of process variations.
Microelectronics Journal, 2008

Controllability of Static CMOS Circuits for Timing Characterization.
J. Electronic Testing, 2008

Performance-Optimized Design for Parametric Reliability.
J. Electronic Testing, 2008

Sequential equivalence checking between system level and RTL descriptions.
Design Autom. for Emb. Sys., 2008

Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Parallel Loopback Test of Mixed-Signal Circuits.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A timing methodology considering within-die clock skew variations.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

On-chip Programmable Capture for Accurate Path Delay Test and Characterization.
Proceedings of the 2008 IEEE International Test Conference, 2008

Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Characterization of Standard Cells for Intra-Cell Mismatch Variations.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Cache Design for Low Power and High Yield.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Budget-Dependent Control-Flow Error Detection.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Adaptive SRAM memory for low power and high yield.
Proceedings of the 26th International Conference on Computer Design, 2008

On efficient generation of instruction sequences to test for delay defects in a processor.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Critical Path Selection for Delay Test Considering Coupling Noise.
Proceedings of the 13th European Test Symposium, 2008

Jitter Decomposition in High-Speed Communication Systems.
Proceedings of the 13th European Test Symposium, 2008

A low-cost concurrent error detection technique for processor control logic.
Proceedings of the Design, Automation and Test in Europe, 2008

Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

Implications of Technology Trends on System Dependability.
Proceedings of the Design, Automation and Test in Europe, 2008

Analytical model for the impact of multiple input switching noise on timing.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems.
IEEE Trans. Computers, 2007

Improved verification of hardware designs through antecedent conditioned slicing.
STTT, 2007

Predicting mixed-signal dynamic performance using optimised signature-based alternate test.
IET Computers & Digital Techniques, 2007

Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Efficient Microprocessor Verification using Antecedent Conditioned Slicing.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

ACCE: Automatic correction of control-flow errors.
Proceedings of the 2007 IEEE International Test Conference, 2007

Built-In Test of RF Mixers Using RF Amplitude Detectors.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Small-Delay Defect Detection in the Presence of Process Variations.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Estimating path delay distribution considering coupling noise.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Reducing verification overhead with RTL slicing.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Automatic Generation of Instructions to Robustly Test Delay Defects in Processors.
Proceedings of the 12th European Test Symposium, 2007

2006
Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Scheme for On-Chip Timing Characterization.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Checking Nested Properties Using Bounded Model Checking and Sequential ATPG.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Cache Organization for Embeded Processors: CAM-vs-SRAM.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Delay Constrained Register Transfer Level Dynamic Power Estimation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Automatic decomposition for sequential equivalence checking of system level and RTL descriptions.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Built-in Fault Diagnosis for Tunable Analog Systems Using an Ensemble Method.
Proceedings of the 2006 IEEE International Test Conference, 2006

HDL Program Slicing to Reduce Bounded Model Checking Search Overhead.
Proceedings of the 2006 IEEE International Test Conference, 2006

Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor.
Proceedings of the 2006 IEEE International Test Conference, 2006

Jitter Decomposition by Time Lag Correlation.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

CEDA: Control-flow Error Detection through Assertions.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Taming the Complexity of STE-based Design Verification Using Program Slicing.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters.
Proceedings of the 11th European Test Symposium, 2006

Adaptive Design for Performance-Optimized Robustness.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Automatic insertion of low power annotations in RTL for pipelined microprocessors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Jitter decomposition in ring oscillators.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor.
Formal Methods in System Design, 2005

Efficient Model Checking of Hardware Using Conditioned Slicing.
Electr. Notes Theor. Comput. Sci., 2005

Automated mapping of pre-computed module-level test sequences to processor instructions.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Testing and debugging delay faults in dynamic circuits.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

An Emulation Model for Sequential ATPG-Based Bounded Model Checking.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Subband filtering for time and frequency analysis of mixed-signal circuit testing.
IEEE Trans. Instrumentation and Measurement, 2004

Prediction of Analog Performance Parameters Using Oscillation Based Test.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Program Slicing for ATPG-Based Property Checking.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Towards The Complete Elimination of Gate/Switch Level Simulations.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Performance Characterization of Mixed-Signal Circuits Using a Ternary Signal Representation.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Formal Verification of a System-on-Chip Using Computation Slicing.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

A low latency and low power dynamic Carry Save Adder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Static program transformations for efficient software model checking.
Proceedings of the Building the Information Society, 2004

LFSR-based BIST for analog circuits using slope detection.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

On-chip delay measurement for silicon debug.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

An efficient linearity test for on-chip high speed ADC and DAC using loop-back.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Delay fault testing and silicon debug using scan chains.
Proceedings of the 9th European Test Symposium, 2004

Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Test data compression and test time reduction using an embedded microprocessor.
IEEE Trans. VLSI Syst., 2003

A comprehensive signature analysis scheme for oscillation-test.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages.
J. Electronic Testing, 2003

Model Checking of Security Protocols with Pre-configuration.
Proceedings of the Information Security Applications, 4th International Workshop, 2003

DSP-Based Statistical Self Test of On-Chip Converters.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Effects of Multi-cycle Sensitization on Delay Tests.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

On-Line Error Detecting Constant Delay Adder.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Quadruple Time Redundancy Adders.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Efficient loop-back testing of on-chip ADCs and DACs.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table.
Formal Methods in System Design, 2002

Program Slicing for Hierarchical Test Generation.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Optimal BIST Using an Embedded Microprocessor.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Verifying Properties Using Sequential ATPG.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Native Mode Functional Self-Test Generation for Systems-on-Chip.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Test generation for resistive opens in CMOS.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Selective-run built-in self-test using an embedded processor.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Massively Parallel/Reconfigurable Emulation Model for the D-algorithm.
Proceedings of the Field-Programmable Logic and Applications, 2002

A Comprehensive Fault Model for Deep Submicron Digital Circuits.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis.
Proceedings of the 2002 Design, 2002

False timing path identification using ATPG techniques and delay-based information.
Proceedings of the 39th Design Automation Conference, 2002

Property Checking via Structural Analysis.
Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001
Frequency Response Verification of Analog Circuits Using Global Optimization Techniques.
J. Electronic Testing, 2001

Design and Development Paradigm for Industrial Formal Verification CAD Tools.
IEEE Design & Test of Computers, 2001

Communication Space Reduction for Formal Verification of Secure Authentication Protocols.
Proceedings of the Third International Workshop on Advanced Issues of E-Commerce and Web-Based Information Systems (WECWIS '01), 2001

Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them?
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Timing Verification and Delay Test Generation for Hierarchical Designs.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

A language formalism for verification of PowerPCTM custom memories using compositions of abstract specifications.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Full chip false timing path identification: applications to the PowerPCTM microprocessors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation.
Proceedings of the Correct Hardware Design and Verification Methods, 2001

2000
An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation.
J. Electronic Testing, 2000

Validating PowerPC Microprocessor Custom Memories.
IEEE Design & Test of Computers, 2000

A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Validation of PowerPC(tm) Custom Memories using Symbolic Simulation.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Hierarchical Test Generation for Systems On a Chip.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Automatic Validation Test Generation Using Extracted Control Models.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

A Mixed-Signal BIST Scheme with Time-Division Multiplexing (TDM) Comparator and Counters.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Performance and Functional Verification of Microprocessors.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

An Adder Using Charge Sharing and its Application in DRAMs.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Verification of Delta-Sigma Converters Using Adaptive Regression Modeling.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

A novel methodology for hierarchical test generation using functional constraint composition.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Causality based generation of directed test cases.
Proceedings of ASP-DAC 2000, 2000

1999
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection.
IEEE Trans. Parallel Distrib. Syst., 1999

An efficient filter-based approach for combinational verification.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

On Design Validation Using Verification Technology.
J. Electronic Testing, 1999

Verification of Processor Microarchitectures.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Subband filtering scheme for analog and mixed-signal circuit testing.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Critical path identification and delay tests of dynamic circuits.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Position Statement: Increasing Test Coverage in a VLSI Design Course.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Improving Witness Search Using Orders on States.
Proceedings of the IEEE International Conference On Computer Design, 1999

Formal Checking of Properties in Complex Systems Using Abstractions.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Transistor Level Synthesis for Static CMOS Combinational Circuits.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

An Efficient Filter-Based Approach for Combinational Verification.
Proceedings of the 1999 Design, 1999

Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor.
Proceedings of the 36th Conference on Design Automation, 1999

Functional Verification of the Equator MAP1000 Microprocessor.
Proceedings of the 36th Conference on Design Automation, 1999

Detecting False Timing Paths: Experiments on PowerPC Microprocessors.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Signature analysis for analog and mixed-signal circuit test response compaction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Abstraction Techniques for Validation Coverage Analysis and Test Generation.
IEEE Trans. Computers, 1998

Memory Distribution: Techniques and Practice for CAD Applications.
Parallel Computing, 1998

Synthesis of Native Mode Self-Test Programs.
J. Electronic Testing, 1998

Using Verification Technology for Validation Coverage Analysis and Test Generation.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Native mode functional test generation for processors with applications to self test and design validation.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Lightweight guided random simulation.
Proceedings of the Ninth International Symposium on Software Reliability Engineering, 1998

To model check or not to model check.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

High-level design validation and test.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel).
Proceedings of the Digest of Papers: FTCS-28, 1998

1997
Automatic verification of implementations of large circuits against HDL specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions.
IEEE Trans. Computers, 1997

An Efficient Critical Path Tracing Algorithm for Designing High Performance Vlsi Systems.
J. Electronic Testing, 1997

A Novel Solution for Chip-Level Functional Timing Verification.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Microprocessor Test and Validation: Any New Avenues?
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

A Novel Hierarchical Test Generation Method for Processors.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

T4: Verification.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Novel Functional Test Generation Method for Processors Using Commercial ATPG.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Hierarchical Specification of System Behavior.
Proceedings of the 2nd High-Assurance Systems Engineering Workshop (HASE '97), 1997

On Combining Formal and Informal Verification.
Proceedings of the Computer Aided Verification, 9th International Conference, 1997

1996
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes.
IEEE Trans. Computers, 1996

A unified approach for fault simulation of linear mixed-signal circuits.
J. Electronic Testing, 1996

Analog Testing with Time Response Parameters.
IEEE Design & Test of Computers, 1996

A novel test generation approach for parametric faults in linear analog circuits .
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

On More Efficient Combinational ATPG Using Functional Learning.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Practical Test and DFT for Next Generation VLSI.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A Unified Framework for Design Validation and Manufacturing Test.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

A Hierarchal Approach for Power Reduction in VLSI Chips.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995
FERRARI: A Flexible Software-Based Fault and Error Injection System.
IEEE Trans. Computers, 1995

Verification of transient response of linear analog circuits.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Efficient multisine testing of analog circuits.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Efficient variable ordering and partial representation algorithm.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A memory distribution mechanism for object oriented applications.
Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995

Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Automated verification of temporal properties specified as state machines in VHDL.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1994
BiCMOS logic testing.
IEEE Trans. VLSI Syst., 1994

An efficient critical path tracing algorithm for sequential circuits.
Microprocessing and Microprogramming, 1994

Impact of behavioral modifications for testability.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Verification of Circuits Described in VHDL through Extraction of Design Intent.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Architectural Performance Verification: PowerPCTM Processors.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

A Signature Analyzer for Analog and Mixed-signal Circuits.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A new scheme to compute variable orders for binary decision diagrams.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Abstraction of data path registers for multilevel verification of large circuits.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Efficient Algorithmic Circuit Verification Using Indexed BDDs.
Proceedings of the Digest of Papers: FTCS/24, 1994

Microprocessor Testing: Which Technique is Best? (Panel).
Proceedings of the 31st Conference on Design Automation, 1994

1993
Benchmarking Parallel Processing Platforms: An Applications Perspective.
IEEE Trans. Parallel Distrib. Syst., 1993

VLSI logic and fault simulation on general-purpose parallel computers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Concurrent Hierarchical and Multilevel Simulation of VLSI Circuits.
Simulation, 1993

A Framework for Distributed VLSI Simulation on a Network of Workstations.
Simulation, 1993

Fault simulation of linear analog circuits.
J. Electronic Testing, 1993

Optimizations for Behavioral/RTL Simulation.
Proceedings of the Sixth International Conference on VLSI Design, 1993

CHEETA: Composition of Hierarchical Sequential Tests Using ATKET.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Adding capability checks enhances error detection and isolation in object-based systems.
Proceedings of the Fourth International Symposium on Software Reliability Engineering, 1993

AMBIANT: Automatic Generation of Behavioral Modifications for Testability.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

MIXER: Mixed-Signal Fault Simulator.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Fault-based automatic test generator for linear analog circuits.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Impact of Behavioral Learning on the Compilation of Sequential Circuit Tests.
Proceedings of the Digest of Papers: FTCS-23, 1993

DRAFTS: Discretized Analog Circuit Fault Simulator.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

VIPER: An Efficient Vigorously Sensitizable Path Extractor.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Test compaction for sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Probabilistic Evaluation of On-Line Checks in Fault-Tolerant Multiprocessor Systems.
IEEE Trans. Computers, 1992

Probabilistic Verification of Boolean Functions.
Formal Methods in System Design, 1992

Generation and evaluation of current and logic tests for switch-level sequential circuits.
J. Electronic Testing, 1992

Hierarchical fault modeling for analog and mixed-signal circuits.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Sequential Redundancy Identification Using Verification Techniques.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Distributed VLSI Simulation on a Network of Workstations.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

CRIS: a test cultivation program for sequential VLSI circuits.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Automatic test generation for linear digital systems with bi-level search using matrix transform methods.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Compiler-Assisted Static Checkpoint Insertion.
Proceedings of the Digest of Papers: FTCS-22, 1992

FERRARI: A Tool for The Validation of System Dependability Properties.
Proceedings of the Digest of Papers: FTCS-22, 1992

Automatic Test Knowledge Extraction from VHDL (ATKET).
Proceedings of the 29th Design Automation Conference, 1992

1991
Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model.
IEEE Trans. Computers, 1991

Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling.
J. Electronic Testing, 1991

Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors.
Digital Signal Processing, 1991

Hardware Acceleration Alone Will Not Make Fault Grading ULSI a Reality.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Probabilistic Design Verification.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Design and evaluation of fault tolerance techniques for highly parallel architectures.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

Parallel switch-level simulation for VLSI.
Proceedings of the conference on European design automation, 1991

Functional abstraction of logic gates for switch-level simulation.
Proceedings of the conference on European design automation, 1991

1990
Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays.
IEEE Trans. Computers, 1990

The Testability of Generalized Counters Under Multiple Faulty Cells.
IEEE Trans. Computers, 1990

Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor.
IEEE Trans. Computers, 1990

Hierarchical multi-level fault simulation of large systems.
J. Electronic Testing, 1990

Design of a scalable parallel switch-level simulator for VLSI.
Proceedings of the Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, 1990

A study of faulty signatures using a matrix formulation.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Forward Recovery Using Checkpointing in Parallel Systems.
Proceedings of the 1990 International Conference on Parallel Processing, 1990

Fault grading of large digital systems.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

BiCMOS fault models: is stuck-at adequate?
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Automatic classification of node types in switch-level descriptions.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Mixed-Level Sequential Test Generation Using a Nine-Valued Relaxation Algorithm.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Hierarchical design and analysis of fault-tolerant multiprocessor systems using concurrent error detection.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

High level test generation using data flow descriptions.
Proceedings of the European Design Automation Conference, 1990

Derivation of signal flow for switch-level simulation.
Proceedings of the European Design Automation Conference, 1990

Speed Up of Test Generation Using High-Level Primitives.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
An Easily Computed Functional Level Testability Measure.
Proceedings of the Proceedings International Test Conference 1989, 1989

The Economics of Scan Design.
Proceedings of the Proceedings International Test Conference 1989, 1989

Advances in VLSI-Testing.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

Synthesis of delay fault testable combinational logic.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Portable parallel logic and fault simulation.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

A Novel Approach to Accurate Timing Verification Using RTL Descriptions.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Average Interconnection Length and Interconnection Distribution Based on Rent's Rule.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Automatic Generation of Behavioral Models from Switch-Level Descriptions.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Fault-Tolerant FFT Networks.
IEEE Trans. Computers, 1988

DC_IATP : An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests.
Proceedings of the Proceedings International Test Conference 1988, 1988

Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing.
Proceedings of the International Conference on Parallel Processing, 1988

CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Compaction of ATPG-generated test sequences for sequential circuits.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

NCUBE: an automatic test generation program for iterative logic arrays.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

General linear codes for fault-tolerant matrix operations on processor arrays.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

Fault Simulation in a Distributed Environment.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
Comparison and Diagnosis of Large Replicated Files.
IEEE Trans. Software Eng., 1987

Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1987

On the C-Testability of Generalized Counters.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1987

Fault Tolerance Techniques for Systolic Arrays.
IEEE Computer, 1987

1986
FAUST: An MOS Fault Simulator with Timing Information.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1986

Distributed Control of Computer Systems.
IEEE Trans. Computers, 1986

Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems.
IEEE Trans. Computers, 1986

Low-Cost Comparison and Diagnosis of Large Remotely Located Files.
Proceedings of the Fifth Symposium on Reliability in Distributed Software and Database Systems, 1986

A Probabilistic Model of Algorithm-Based Fault Tolerance in Array Processors for Real-Time Systems.
Proceedings of the 7th IEEE Real-Time Systems Symposium (RTSS '86), 1986

Approaches to Circuit Level Design for Testability.
Proceedings of the Proceedings International Test Conference 1986, 1986

Structured Functional Level Test Generation Using Binary Decision Diagrams.
Proceedings of the Proceedings International Test Conference 1986, 1986

Design of Systems with Concurrent Error Detection Using Software Redundancy.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

On the Design of Fault-Tolerant Systolic Arrays with Linear Cells.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

Research in Reliable VLSI Architectures at the University of Illinois.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

Transistor-level test generation for physical failures in CMOS circuits.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985
Design of Testable CMOS Logic Circuits Under Arbitrary Delays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1985

A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1985

CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator.
Proceedings of the Proceedings International Test Conference 1985, 1985

Self-Test for Microprocessors.
Proceedings of the Proceedings International Test Conference 1985, 1985

TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

High level hierarchical fault simulation techniques.
Proceedings of the 13th ACM Annual Conference on Computer Science, 1985

1984
Algorithm-Based Fault Tolerance for Matrix Operations.
IEEE Trans. Computers, 1984

Functional Testing of Microprocessors.
IEEE Trans. Computers, 1984

Design of Test Pattern Generators for Built-In Test.
Proceedings of the Proceedings International Test Conference 1984, 1984

Fault-Secure Algorithms for Multiple-Processor Systems.
Proceedings of the 11th Annual Symposium on Computer Architecture, 1984

1983
Load Redistribution Under Failure in Distributed Systems.
IEEE Trans. Computers, 1983

Generating Tests for Physical Failures in MOS Logic Circuits.
Proceedings of the Proceedings International Test Conference 1983, 1983

Incorporating Test Technology into an Undergraduate Curriculum.
Proceedings of the Proceedings International Test Conference 1983, 1983

Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983

Concurrent Error Detection in VLSI Interconnection Networks
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983

1982
Load Balancing in Distributed Systems.
IEEE Trans. Software Eng., 1982

Using write back cache to improve performance of multi-user multiprocessors.
Proceedings of the International Conference on Parallel Processing, 1982

Efficient parallel algorithms for processor arrays.
Proceedings of the International Conference on Parallel Processing, 1982

Test generation for programmable logic arrays.
Proceedings of the 19th Design Automation Conference, 1982

1981
Design of Testable Structures Defined by Simple Loops.
IEEE Trans. Computers, 1981

Functional Level Test Generation for Complex Digital Systems.
Proceedings of the Proceedings International Test Conference 1981, 1981

1980
Test Generation for Microprocessors.
IEEE Trans. Computers, 1980

1978
Efficient Algorithms for Testing Semiconductor Random-Access Memories.
IEEE Trans. Computers, 1978

1975
A Combinatorial Solution to the Reliability of Interwoven Redundant Logic Networks.
IEEE Trans. Computers, 1975

1974
An Algorithm for the Accurate Reliability Evaluation of Triple Modular Redundancy Networks.
IEEE Trans. Computers, 1974


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