Jacob A. Abraham
Orcid: 0000-0002-5336-5631Affiliations:
- University of Texas at Austin, USA
According to our database1,
Jacob A. Abraham
authored at least 437 papers
between 1974 and 2023.
Collaborative distances:
Collaborative distances:
Awards
ACM Fellow
ACM Fellow 2001, "For outstanding contributions in the fields of fault tolerant computing, automatic test generation and design for test, and formal verification.".
Timeline
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Online presence:
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on orcid.org
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Bibliography
2023
Secure Control Loop Execution of Cyber-Physical Devices Using Predictive State Space Checks.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
2022
Selection scheme sensitivity for a hybrid Salp Swarm Algorithm: analysis and applications.
Eng. Comput., 2022
2021
Real-Time Error Detection in Nonlinear Control Systems Using Machine Learning Assisted State-Space Encoding.
IEEE Trans. Dependable Secur. Comput., 2021
IEEE J. Solid State Circuits, 2021
A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor.
IEEE J. Solid State Circuits, 2021
Training Multi-Bit Quantized and Binarized Networks with a Learnable Symmetric Quantizer.
IEEE Access, 2021
2020
IEEE Access, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the IEEE International Test Conference, 2020
Randomized Pulse-Modulating Instruction-Issue Control Circuit for a Current and Temperature Limiting System in a 7nm Hexagon™ Compute DSP.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Spectral Leakage-Driven Loopback Scheme for Prediction of Mixed-Signal Circuit Specifications.
IEEE Trans. Ind. Electron., 2019
IEEE J. Solid State Circuits, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Design of efficient error resilience in signal processing and control systems: From algorithms to circuits.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Design of Self Calibrating and Error Resilient Mixed-Signal Systems for Signal Processing, Communications and Control.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Checksum based error detection in linearized representations of non linear control systems.
Proceedings of the 17th Latin-American Test Symposium, 2016
Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states.
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016
Clear: c̲ross-l̲ayer e̲xploration for a̲rchitecting r̲esilience combining hardware and software techniques to tolerate soft errors in processor cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
IEICE Trans. Electron., 2015
J. Electron. Test., 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Tutorial T3: Error Resilient Real-Time Embedded Systems: Computing, Communications and Control.
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Power-aware multi-voltage custom memory models for enhancing RTL and low power verification.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Bitstream-Driven Built-In Characterization for Analog and Mixed-Signal Embedded Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players?
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the 15th Latin American Test Workshop, 2014
EAGLE: A regression model for fault coverage estimation using a simulation based metric.
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014
Connecting different worlds - Technology abstraction for reliability-aware design and Test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Asynchronous Measurement of Transient Phase-Shift Resulting From RF Receiver State-Change.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
A framework for low overhead hardware based runtime control flow error detection and recovery.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faults.
Proceedings of the 2013 IEEE International Test Conference, 2013
On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
A reduced voltage swing circuit using a single supply to enable lower voltage operation for SRAM-based memory.
Microelectron. J., 2012
Automatic and Correct Register Transfer Level Annotations for Low Power Microprocessor Design.
J. Low Power Electron., 2012
J. Circuits Syst. Comput., 2012
J. Electron. Test., 2012
J. Electron. Test., 2012
J. Electron. Test., 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management.
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Stream cipher hash based execution monitoring (SCHEM) framework for intrusion detection on embedded processors.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Functional test generation for hard to detect stuck-at faults using RTL model checking.
Proceedings of the 17th IEEE European Test Symposium, 2012
Indirect method for random jitter measurement on SoCs using critical path characterization.
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Transformer-Coupled Loopback Test for Differential Mixed-Signal Dynamic Specifications.
IEEE Trans. Instrum. Meas., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Pseudorandom Test of Nonlinear Analog and Mixed-Signal Circuits Based on a Volterra Series Model.
J. Electron. Test., 2011
Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip.
J. Electron. Test., 2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits.
J. Electron. Test., 2010
J. Electron. Test., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPM.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the International Joint Conference on Neural Networks, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 15th European Test Symposium, 2010
Calibration-enabled scalable built-in current sensor compatible with very low cost ATE.
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces.
Proceedings of the 19th IEEE Asian Test Symposium, 2010
A novel characterization technique for high speed I/O mixed signal circuit components using random jitter injection.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level.
J. Low Power Electron., 2009
J. Electron. Test., 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Hybrid BiST Solution for Analog to Digital Converters with Low-cost Automatic Test Equipment Compatibility.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 27th International Conference on Computer Design, 2009
A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 14th IEEE European Test Symposium, 2009
Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip.
Proceedings of the 14th IEEE European Test Symposium, 2009
SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits.
Proceedings of the Eighteentgh Asian Test Symposium, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
Microelectron. J., 2008
J. Electron. Test., 2008
Des. Autom. Embed. Syst., 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 26th International Conference on Computer Design, 2008
On efficient generation of instruction sequences to test for delay defects in a processor.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems.
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems.
IEEE Trans. Computers, 2007
Int. J. Softw. Tools Technol. Transf., 2007
Predicting mixed-signal dynamic performance using optimised signature-based alternate test.
IET Comput. Digit. Tech., 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 12th European Test Symposium, 2007
2006
Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor.
Proceedings of the 2006 IEEE International Test Conference, 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006
Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters.
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
A Statistical Digital Equalizer for Loopback-based Linearity Test of Data Converters.
Proceedings of the 15th Asian Test Symposium, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor.
Formal Methods Syst. Des., 2005
Automated mapping of pre-computed module-level test sequences to processor instructions.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
2004
IEEE Trans. Instrum. Meas., 2004
Proceedings of the Fouth International Workshop on Automated Verification of Critical Systems, 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Performance Characterization of Mixed-Signal Circuits Using a Ternary Signal Representation.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
A low latency and low power dynamic Carry Save Adder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the Building the Information Society, 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 9th European Test Symposium, 2004
Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages.
J. Electron. Test., 2003
Proceedings of the Information Security Applications, 4th International Workshop, 2003
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Formal Methods Syst. Des., 2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis.
Proceedings of the 2002 Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
Proceedings of the Computer Aided Verification, 14th International Conference, 2002
2001
Frequency Response Verification of Analog Circuits Using Global Optimization Techniques.
J. Electron. Test., 2001
IEEE Des. Test Comput., 2001
Communication Space Reduction for Formal Verification of Secure Authentication Protocols.
Proceedings of the Third International Workshop on Advanced Issues of E-Commerce and Web-Based Information Systems (WECWIS '01), 2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
A language formalism for verification of PowerPC<sup>TM</sup> custom memories using compositions of abstract specifications.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001
Full chip false timing path identification: applications to the PowerPCTM microprocessors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Using Abstract Specifications to Verify PowerPC<sup>TM</sup> Custom Memories by Symbolic Trajectory Evaluation.
Proceedings of the Correct Hardware Design and Verification Methods, 2001
2000
An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation.
J. Electron. Test., 2000
A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
A Mixed-Signal BIST Scheme with Time-Division Multiplexing (TDM) Comparator and Counters.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
A Quick and Inexpensive Method to Identify False Critical Paths Using ATPG Techniques: an Experiment with a PowerPC Microprocessor.
Proceedings of the 1st Latin American Test Workshop, 2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
A novel methodology for hierarchical test generation using functional constraint composition.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000
Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPC<sup>TM</sup> microprocessor.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection.
IEEE Trans. Parallel Distributed Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor.
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
IEEE Trans. Computers, 1998
Parallel Comput., 1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Native mode functional test generation for processors with applications to self test and design validation.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the Ninth International Symposium on Software Reliability Engineering, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel).
Proceedings of the Digest of Papers: FTCS-28, 1998
1997
Automatic verification of implementations of large circuits against HDL specifications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions.
IEEE Trans. Computers, 1997
An Efficient Critical Path Tracing Algorithm for Designing High Performance Vlsi Systems.
J. Electron. Test., 1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
Proceedings of the 2nd High-Assurance Systems Engineering Workshop (HASE '97), 1997
Proceedings of the Computer Aided Verification, 9th International Conference, 1997
1996
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes.
IEEE Trans. Computers, 1996
J. Electron. Test., 1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996
1995
IEEE Trans. Computers, 1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995
Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995
1994
Microprocess. Microprogramming, 1994
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
Proceedings of the Seventh International Conference on VLSI Design, 1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994
Proceedings of the Digest of Papers: FTCS/24, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1993
IEEE Trans. Parallel Distributed Syst., 1993
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
Simul., 1993
Generation of testable designs from behavioral descriptions using high level synthesis tools.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993
Proceedings of the Sixth International Conference on VLSI Design, 1993
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
Adding capability checks enhances error detection and isolation in object-based systems.
Proceedings of the Fourth International Symposium on Software Reliability Engineering, 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the Digest of Papers: FTCS-23, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor.
Proceedings of the 30th Design Automation Conference. Dallas, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1992
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
IEEE Trans. Computers, 1992
Generation and evaluation of current and logic tests for switch-level sequential circuits.
J. Electron. Test., 1992
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992
Automatic test generation for linear digital systems with bi-level search using matrix transform methods.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992
Proceedings of the Digest of Papers: FTCS-22, 1992
Proceedings of the Digest of Papers: FTCS-22, 1992
Proceedings of the 29th Design Automation Conference, 1992
1991
IEEE Trans. Computers, 1991
Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling.
J. Electron. Test., 1991
Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors.
Digit. Signal Process., 1991
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991
High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991
Design and evaluation of fault tolerance techniques for highly parallel architectures.
Proceedings of the First Great Lakes Symposium on VLSI, 1991
Proceedings of the conference on European design automation, 1991
Proceedings of the conference on European design automation, 1991
1990
IEEE Trans. Computers, 1990
IEEE Trans. Computers, 1990
IEEE Trans. Computers, 1990
Proceedings of the Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, 1990
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990
Forward Recovery Using Checkpointing in Parallel Systems.
Proceedings of the 1990 International Conference on Parallel Processing, 1990
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
Hierarchical design and analysis of fault-tolerant multiprocessor systems using concurrent error detection.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990
Proceedings of the European Design Automation Conference, 1990
Proceedings of the European Design Automation Conference, 1990
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990
1989
Proceedings of the Proceedings International Test Conference 1989, 1989
Proceedings of the Proceedings International Test Conference 1989, 1989
Advances in VLSI-Testing.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989
Average Interconnection Length and Interconnection Distribution Based on Rent's Rule.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989
1988
DC_IATP : An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests.
Proceedings of the Proceedings International Test Conference 1988, 1988
Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing.
Proceedings of the International Conference on Parallel Processing, 1988
CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988
Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988
1987
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987
1986
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986
IEEE Trans. Computers, 1986
Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures.
Proc. IEEE, 1986
Low-Cost Comparison and Diagnosis of Large Remotely Located Files.
Proceedings of the Fifth Symposium on Reliability in Distributed Software and Database Systems, 1986
A Probabilistic Model of Algorithm-Based Fault Tolerance in Array Processors for Real-Time Systems.
Proceedings of the 7th IEEE Real-Time Systems Symposium (RTSS '86), 1986
Approaches to Circuit Level Design for Testability.
Proceedings of the Proceedings International Test Conference 1986, 1986
Structured Functional Level Test Generation Using Binary Decision Diagrams.
Proceedings of the Proceedings International Test Conference 1986, 1986
Design of Systems with Concurrent Error Detection Using Software Redundancy.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986
On the Design of Fault-Tolerant Systolic Arrays with Linear Cells.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986
Research in Reliable VLSI Architectures at the University of Illinois.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986
1985
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985
CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator.
Proceedings of the Proceedings International Test Conference 1985, 1985
Self-Test for Microprocessors.
Proceedings of the Proceedings International Test Conference 1985, 1985
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985
Proceedings of the 13th ACM Annual Conference on Computer Science, 1985
1984
IEEE Des. Test, 1984
Design of Test Pattern Generators for Built-In Test.
Proceedings of the Proceedings International Test Conference 1984, 1984
Proceedings of the 11th Annual Symposium on Computer Architecture, 1984
1983
IEEE Trans. Computers, 1983
Generating Tests for Physical Failures in MOS Logic Circuits.
Proceedings of the Proceedings International Test Conference 1983, 1983
Incorporating Test Technology into an Undergraduate Curriculum.
Proceedings of the Proceedings International Test Conference 1983, 1983
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983
1982
Using write back cache to improve performance of multi-user multiprocessors.
Proceedings of the International Conference on Parallel Processing, 1982
Efficient parallel algorithms for processor arrays.
Proceedings of the International Conference on Parallel Processing, 1982
Proceedings of the 19th Design Automation Conference, 1982
1981
Functional Level Test Generation for Complex Digital Systems.
Proceedings of the Proceedings International Test Conference 1981, 1981
1980
1978
IEEE Trans. Computers, 1978
1975
IEEE Trans. Computers, 1975
1974
An Algorithm for the Accurate Reliability Evaluation of Triple Modular Redundancy Networks.
IEEE Trans. Computers, 1974