Chia-Tsun Wu

According to our database, Chia-Tsun Wu authored at least 4 papers between 2005 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2010

A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm.

Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, An-Yeu Wu

IEEE Trans. Circuits Syst. II Express Briefs, 2010

2006

A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time.

Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A portable all-digital pulsewidth control loop for SOC applications.

Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A scalable DCO design for portable ADPLL designs.

Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005