Chiao-Yun Tu

According to our database1, Chiao-Yun Tu authored at least 2 papers in 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2014
Designing Coalescing Network-on-Chip for Efficient Memory Accesses of GPGPUs.
Proceedings of the Network and Parallel Computing, 2014

Traffic-aware frequency scaling for balanced on-chip networks on GPGPUs.
Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014


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