Chih-Hsiu Lin

According to our database, Chih-Hsiu Lin authored at least 6 papers between 2003 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2006

High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems.

Chih-Hsiu Lin, An-Yeu Wu, Fan-Min Li

IEEE Trans. Circuits Syst. II Express Briefs, 2006

2005

Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture.

Chih-Hsiu Lin, An-Yeu Wu

IEEE Trans. Signal Process., 2005

Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications.

Chih-Hsiu Lin, An-Yeu Wu

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Low cost decision feedback equalizer (DFE) design for Giga-bit systems.

Chih-Hsiu Lin, An-Yeu Wu

Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

2003

A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes.

Cheng-Shing Wu, An-Yeu Wu, Chih-Hsiu Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2003

VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems.

Jen-Chih Kuo, Ching-Hua Wen, Chih-Hsiu Lin, An-Yeu Wu

EURASIP J. Adv. Signal Process., 2003