Chih-Ting Yeh
According to our database1,
Chih-Ting Yeh
authored at least 14 papers
between 2008 and 2023.
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Bibliography
2023
Proceedings of the IEEE International Conference on Web Intelligence and Intelligent Agent Technology, 2023
2021
A Learning Framework with Disposable Auxiliary Networks for Early Prediction of Product Success.
Proceedings of the WI-IAT '21: IEEE/WIC/ACM International Conference on Web Intelligence, Melbourne VIC Australia, December 14, 2021
An Exploration Study of Multi-stage Conversational Passage Retrieval: Paraphrase Query Expansion and Multi-view Point-wise Ranking.
Proceedings of the Thirtieth Text REtrieval Conference, 2021
2019
以三元組損失微調時延神經網路語者嵌入函數之語者辨識系統(Time Delay Neural Network-based Speaker Embedding Function Fine-tuned with Triplet Loss for Distance-based Speaker Recognition).
Proceedings of the 31st Conference on Computational Linguistics and Speech Processing, 2019
Proceedings of the IEEE International Conference on Acoustics, 2019
2018
結合卷積神經網路與遞迴神經網路於推文極性分類 (Combining Convolutional Neural Network and Recurrent Neural Network for Tweet Polarity Classification) [In Chinese].
Proceedings of the 30th Conference on Computational Linguistics and Speech Processing, 2018
2013
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit.
Microelectron. Reliab., 2013
Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
2012
New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications.
Microelectron. Reliab., 2012
New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
2011
Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection.
IEEE J. Solid State Circuits, 2010
2008
Active ESD protection design against cross-power-domain ESD stresses in CMOS integrated circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008