Ming-Dou Ker
Orcid: 0000-0003-3622-181X
According to our database1,
Ming-Dou Ker
authored at least 181 papers
between 1995 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2008, "For contributions to electrostatic protection in integrated circuits, and performance optimization of VLSI micro-systems".
Timeline
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Bibliography
2023
Design of Dual-Configuration Dual-Mode Stimulator in Low-Voltage CMOS Process for Neuro-Modulation.
IEEE Trans. Biomed. Circuits Syst., April, 2023
A CMOS Synchronized Sample-and-Hold Artifact Blanking Analog Front-End Local Field Potential Acquisition Unit With ±3.6-V Stimulation Artifact Tolerance and Monopolar Electrode-Tissue Impedance Measurement Circuit for Closed-Loop Deep Brain Stimulation SoCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
Investigation of Safe Operating Area on 4H-SiC 600V VDMOSFET with TLP and UIS Test Methods.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
2021
Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process.
IEEE Trans. Biomed. Circuits Syst., 2021
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification.
IEEE J. Solid State Circuits, 2021
Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON Events.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021
Proceedings of the 17th International Conference on Machine Vision and Applications, 2021
Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
2020
Design of Stage-Selective Negative Voltage Generator to Improve On-Chip Power Conversion Efficiency for Neuron Stimulation.
IEEE Trans. Circuits Syst., 2020
Design of Dual-Mode Stimulus Chip With Built-In High Voltage Generator for Biomedical Applications.
IEEE Trans. Biomed. Circuits Syst., 2020
Over-Voltage Protection on the CC Pin of USB Type-C Interface against Electrical Overstress Events.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Trans. Biomed. Eng., 2019
IEEE Trans. Biomed. Circuits Syst., 2019
ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
2018
Surge protection design with surge-to-digital converter for microelectronic circuits and systems.
Microelectron. Reliab., 2018
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control.
IEEE J. Solid State Circuits, 2018
A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process.
IEEE Trans. Biomed. Circuits Syst., 2017
Microelectron. Reliab., 2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
An Ultra-Low Voltage CMOS Voltage Controlled Oscillator with Process and Temperature Compensation.
IEICE Trans. Electron., 2017
Design considerations and clinical applications of closed-loop neural disorder control SoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process.
IEEE Trans. Biomed. Circuits Syst., 2016
Design of high-voltage-tolerant level shifter in low voltage CMOS process for neuro stimulator.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
2015
Proceedings of the VLSI Design, Automation and Test, 2015
ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits.
Proceedings of the European Conference on Circuit Theory and Design, 2015
Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection.
Proceedings of the European Conference on Circuit Theory and Design, 2015
2014
On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection.
IEEE Trans. Ind. Electron., 2014
SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance.
Microelectron. Reliab., 2014
Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit.
Microelectron. Reliab., 2014
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control.
IEEE J. Solid State Circuits, 2014
Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Design of 2 × V<sub>DD</sub>-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 × V<sub>DD</sub> Thin-Oxide Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Implantable Stimulator for Epileptic Seizure Suppression With Loading Impedance Adaptability.
IEEE Trans. Biomed. Circuits Syst., 2013
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit.
Microelectron. Reliab., 2013
Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
New 4-Bit Transient-to-Digital Converter for System-Level ESD Protection in Display Panels.
IEEE Trans. Ind. Electron., 2012
New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications.
Microelectron. Reliab., 2012
Microelectron. Reliab., 2012
New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
High-voltage-tolerant stimulator with adaptive loading consideration for electronic epilepsy prosthetic SoC in a 0.18-µm CMOS process.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
New design of transient-noise detection circuit with SCR device for system-level ESD protection.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Live demonstration: Implantable stimulator for epileptic seizure suppression with loading impedance adaptability.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
Design of negative high voltage generator for biphasic stimulator with soc integration consideration.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
Design of ESD protection for RF CMOS power amplifier with inductor in matching network.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process.
Microelectron. Reliab., 2011
Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process.
Microelectron. Reliab., 2011
Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs.
IEEE J. Solid State Circuits, 2011
Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance.
IEEE Trans. Ind. Electron., 2010
Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation.
Microelectron. Reliab., 2010
Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme.
Microelectron. Reliab., 2010
Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-µm CMOS technology.
Microelectron. Reliab., 2010
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection.
IEEE J. Solid State Circuits, 2010
2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process.
Microelectron. Reliab., 2009
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology.
IEEE J. Solid State Circuits, 2009
IEICE Trans. Electron., 2009
On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test.
IEEE J. Solid State Circuits, 2008
IEICE Trans. Electron., 2008
Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process.
IEICE Trans. Electron., 2008
2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Design of bandgap voltage reference circuit with all TFT devices on glass substrate in a 3-μm LTPS process.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology.
Microelectron. Reliab., 2007
Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits.
Microelectron. Reliab., 2007
Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology.
IEEE J. Solid State Circuits, 2007
ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process.
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A New Architecture for Charge Pump Circuit Without Suffering Gate-Oxide Reliability in Low-Voltage CMOS Processes.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Design of 2�?VDD-Tolerant I/O Buffer with Considerations of Gate-Oxide Reliability and Hot-Carrier Degradation.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board.
Microelectron. Reliab., 2006
ESD robustness of thin-film devices with different layout structures in LTPS technology.
Microelectron. Reliab., 2006
Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology.
Microelectron. Reliab., 2006
Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes.
IEEE J. Solid State Circuits, 2006
Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices.
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Design on new tracking circuit of I/O buffer in 0.13µm cell library for mixed-voltage application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
A new Schmitt trigger circuit in a 0.13-μm 1/2.5-V CMOS process to receive 3.3-V input signals.
IEEE Trans. Circuits Syst. II Express Briefs, 2005
Investigation on seal-ring rules for IC product reliability in 0.25-mum CMOS technology.
Microelectron. Reliab., 2005
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology.
IEEE J. Solid State Circuits, 2005
The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs.
IEEE J. Solid State Circuits, 2005
IEICE Trans. Electron., 2005
A CMOS Bandgap Reference Circuit for Sub-1-V Operation without Using Extra Low-Threshold-Voltage Device.
IEICE Trans. Electron., 2005
ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Microelectron. Reliab., 2004
IEEE J. Solid State Circuits, 2004
Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
ESD protection design for IC with power-down-mode operation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Analysis and Prevention on NC-ball induced ESD Damages in a 683-Pin BGA Packaged Chipset IC.
Microelectron. Reliab., 2003
Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product.
Microelectron. Reliab., 2003
Latchup-free ESD protection design with complementary substrate-triggered SCR devices.
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
Microelectron. Reliab., 2002
IEEE J. Solid State Circuits, 2002
ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard.
Microelectron. Reliab., 2001
IEEE J. Solid State Circuits, 2001
Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
2000
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process.
IEEE J. Solid State Circuits, 2000
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications.
IEEE J. Solid State Circuits, 2000
Mew diode string design with very low leakage current for using in power supply ESD clamp circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Electrostatic discharge protection circuits in CMOS IC's using the lateral SCR devices: an overview.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1997
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs.
IEEE J. Solid State Circuits, 1997
ESD protection for CMOS output buffer by using modified LVTSCR devices with high trigger current.
IEEE J. Solid State Circuits, 1997
1996
IEEE Trans. Very Large Scale Integr. Syst., 1996
1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995