Chun-Hsian Huang

According to our database1, Chun-Hsian Huang authored at least 27 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Adaptive and service-oriented embedded system for information security applications.
Comput. Electr. Eng., 2019

2018
Hierarchical and Dependency-Aware Task Mapping for NoC-based Systems.
Proceedings of the 11th International Workshop on Network on Chip Architectures, 2018

2017
Elastic superposition task mapping for NoC-based reconfigurable systems.
Microprocess. Microsystems, 2017

2016
Introduction to the special issue on smart reconfigurable system modeling, design, and implementation.
Microprocess. Microsystems, 2016

Introduction to the special issue on reconfigurable cyber-physical and embedded system design.
J. Syst. Archit., 2016

2015
Virtualization Architecture for NoC-based Reconfigurable Systems.
CoRR, 2015

A Self-Adaptive System for Vehicle Information Security Applications.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

2014
A reconfigurable point target detection system based on morphological clutter elimination.
J. Syst. Archit., 2014

2013
Virtualizable hardware/software design infrastructure for dynamically partially reconfigurable systems.
TRETS, 2013

Learning-based adaptation to applications and environments in a reconfigurable network-on-chip for reducing crosstalk and dynamic power consumption.
Comput. Electr. Eng., 2013

An FPGA-based point target detection system using morphological clutter elimination.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2011
Model-Based Verification and Estimation Framework for Dynamically Partially Reconfigurable Systems.
IEEE Trans. Industrial Informatics, 2011

2010
Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems.
TRETS, 2010

Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption.
J. Syst. Archit., 2010

UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems.
J. Syst. Archit., 2010

A Self-Adaptive Hardware/Software System Architecture for Ubiquitous Computing Applications.
Proceedings of the Ubiquitous Intelligence and Computing - 7th International Conference, 2010

Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Modeling and verification of real-time embedded systems with urgency.
J. Syst. Softw., 2009

Hardware task scheduling and placement in operating systems for dynamically reconfigurable SoC.
J. Embedded Computing, 2009

Hardware Resource Virtualization for Dynamically Partially Reconfigurable Systems.
Embedded Systems Letters, 2009

On the Use of a UML-Based HW/SW Co-Design Platform for Reconfigurable Cryptographic Systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Software-Controlled Dynamically Swappable Hardware Design in Partially Reconfigurable Systems.
EURASIP J. Emb. Sys., 2008

UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems.
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008

2007
Dynamically Swappable Hardware Design in Partially Reconfigurable Systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Perfecto: A Systemc-Based Performance Evaluation Framework for Dynamically Partially Reconfigurable Systems.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Model Checking Timed Systems with Urgencies.
Proceedings of the Automated Technology for Verification and Analysis, 2006

2005
Model Checking Prioritized Timed Automata.
Proceedings of the Automated Technology for Verification and Analysis, 2005


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