Jih-Sheng Shen
According to our database1,
Jih-Sheng Shen
authored at least 19 papers
between 2005 and 2014.
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Bibliography
2014
Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Dynamic partially reconfigurable architecture for fast Fourier transform computation.
Int. J. Embed. Syst., 2014
Reconfigurable Network-on-chip design for heterogeneous multi-core system architecture.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014
2013
Learning-based adaptation to applications and environments in a reconfigurable network-on-chip for reducing crosstalk and dynamic power consumption.
Comput. Electr. Eng., 2013
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems.
ACM Trans. Reconfigurable Technol. Syst., 2010
Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption.
J. Syst. Archit., 2010
UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems.
J. Syst. Archit., 2010
A Self-Adaptive Hardware/Software System Architecture for Ubiquitous Computing Applications.
Proceedings of the Ubiquitous Intelligence and Computing - 7th International Conference, 2010
Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip.
Proceedings of the Design, Automation and Test in Europe, 2010
Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication.
IGI Global, ISBN: 978-1-61520-807-4, 2010
2008
Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes.
ACM Trans. Design Autom. Electr. Syst., 2008
A novel spatio-temporal adaptive bus encoding for reducing crosstalk interferences with trade-offs between performance and reliability.
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs.
Proceedings of the 43rd Design Automation Conference, 2006
Fast Run-Time Power Monitoring Methodology for Embedded Systems.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006
2005
A low-power crossroad switch architecture and its core placement for network-on-chip.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Crossroad System-on-Chip Communication Architecture for Low Power Embedded Systems.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005