Chung-Jay Yang

According to our database¹, Chung-Jay Yang authored at least 9 papers between 2008 and 2013.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Bibliography

2013

A High-Throughput Trellis-Based Layered Decoding Architecture for Non-Binary LDPC Codes Using Max-Log-QSPA.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2013

An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shuffled Decoding.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012

Jointly Designed Architecture-Aware LDPC Convolutional Codes and Memory-Based Shuffled Decoder Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2012

An Efficient Layered Decoding Architecture for Nonbinary QC-LDPC Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011

Processing-Task Arrangement for a Low-Complexity Full-Mode WiMAX LDPC Codec.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A selective-input non-binary LDPC decoder architecture.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2011

2010

A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009

A Shuffled Message-passing Decoding Method for Memory-based LDPC Decoders.

[BibT_eX]

[DOI]

Yeong-Luh Ueng

Chung-Jay Yang

Chun-Jung Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Chung-Jay Yang

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