Cindy Eisner

According to our database1, Cindy Eisner authored at least 28 papers between 1996 and 2018.

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PhD thesis 


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Functional Specification of Hardware via Temporal Logic.
Proceedings of the Handbook of Model Checking., 2018

Accurate Malware Detection by Extreme Abstraction.
Proceedings of the 34th Annual Computer Security Applications Conference, 2018

Safety and Liveness, Weakness and Strength, and the Underlying Topological Relations.
ACM Trans. Comput. Log., 2014

Relative Equivalence in the Presence of Ambiguity.
Proceedings of the Computer Aided Verification - 25th International Conference, 2013

Functional verification of power gated designs by compositional reasoning.
Formal Methods Syst. Des., 2009

Resurrecting infeasible clock-gating functions.
Proceedings of the 46th Design Automation Conference, 2009

Policy Validation for System Automation: A Case Study.
Proceedings of the 9th IEEE International Workshop on Policies for Distributed Systems and Networks (POLICY 2008), 2008

Structural Contradictions.
Proceedings of the Hardware and Software: Verification and Testing, 2008

Augmenting a Regular Expression-Based Temporal Logic with Local Variables.
Proceedings of the Formal Methods in Computer-Aided Design, 2008

PSL for Runtime Verification: Theory and Practice.
Proceedings of the Runtime Verification, 7th International Workshop, 2007

A Practical Introduction to PSL
Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-36123-9, 2006

ExpliSAT: Guiding SAT-Based Software Verification with Explicit States.
Proceedings of the Hardware and Software, 2006

Formal verification of software source code through semi-automatic modeling.
Softw. Syst. Model., 2005

A topological characterization of weakness.
Proceedings of the Twenty-Fourth Annual ACM Symposium on Principles of Distributed Computing, 2005

Model Checking at IBM.
Formal Methods Syst. Des., 2003

The Definition of a Temporal Clock Operator.
Proceedings of the Automata, Languages and Programming, 30th International Colloquium, 2003

Reasoning with Temporal Logic on Truncated Paths.
Proceedings of the Computer Aided Verification, 15th International Conference, 2003

Using symbolic CTL model checking to verify the railway stations of Hoorn-Kersenboogerd and Heerhugowaard.
Int. J. Softw. Tools Technol. Transf., 2002

Comparing Symbolic and Explicit Model Checking of a Software System.
Proceedings of the Model Checking of Software, 2002

Efficient Detection of Vacuity in Temporal Model Checking.
Formal Methods Syst. Des., 2001

On the Effective Deployment of Functional Formal Verification.
Formal Methods Syst. Des., 2001

Model checking the garbage collection mechanism of SMV.
Electron. Notes Theor. Comput. Sci., 2001

The Temporal Logic Sugar.
Proceedings of the Computer Aided Verification, 13th International Conference, 2001

A methodology for formal design of hardware control with application to cache coherence protocols.
Proceedings of the 37th Conference on Design Automation, 2000

Using Symbolic Model Checking to Verify the Railway Stations of Hoorn-Kersenboogerd and Heerhugowaard.
Proceedings of the Correct Hardware Design and Verification Methods, 1999

Efficient Detection of Vacuity in ACTL Formulaas.
Proceedings of the Computer Aided Verification, 9th International Conference, 1997

RuleBase: Model Checking at IBM.
Proceedings of the Computer Aided Verification, 9th International Conference, 1997

RuleBase: An Industry-Oriented Formal Verification Tool.
Proceedings of the 33st Conference on Design Automation, 1996