Congyuan Xu

According to our database, Congyuan Xu authored at least 13 papers between 2015 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

DELP-Net: A Differentiable Entropy Layer Pyramid Network for End-to-End Low-Rate DoS Detection.

Jinyi Wang, Congyuan Xu, Jun Yang

Entropy, 2026

2025

A subspace-based few-shot intrusion detection system for the Internet of Things.

Zhihui Li, Congyuan Xu, Kun Deng, Chunyuan Liu

Frontiers Inf. Technol. Electron. Eng., June, 2025

2024

Design and Implementation of Automatic Punching Management System Based on Computer Vision.

Gang Ke, Shi Wang, Jun Yang, Xiaoyun Xia, Congyuan Xu, Feng Liu

J. Inf. Sci. Eng., May, 2024

2021

Low-rate DoS attack detection method based on hybrid deep neural networks.

Congyuan Xu, Jizhong Shen, Xin Du

J. Inf. Secur. Appl., 2021

2020

A Method of Few-Shot Network Intrusion Detection Based on Meta-Learning Framework.

Congyuan Xu, Jizhong Shen, Xin Du

IEEE Trans. Inf. Forensics Secur., 2020

2019

Detection method of domain names generated by DGAs based on semantic representation and deep neural network.

Congyuan Xu, Jizhong Shen, Xin Du

Comput. Secur., 2019

2018

An Intrusion Detection System Using a Deep Neural Network With Gated Recurrent Units.

Congyuan Xu, Jizhong Shen, Xin Du, Fan Zhang

IEEE Access, 2018

Optimized Lightweight Hardware Trojan-Based Fault Attack on DES.

Fan Zhang, Yiran Zhang, Shengwen Shi, Shize Guo, Ziyuan Liang, Samiya Qureshi, Congyuan Xu

Proceedings of the 24th IEEE International Conference on Parallel and Distributed Systems, 2018

2017

Function synthesis algorithm based on RTD-based three-variable universal logic gates.

Maoqun Yao, Kai Yang, Jizhong Shen, Congyuan Xu

Frontiers Inf. Technol. Electron. Eng., 2017

2016

Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme.

Liang Geng, Jizhong Shen, Congyuan Xu

Frontiers Inf. Technol. Electron. Eng., 2016

Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications.

Liang Geng, Jizhong Shen, Congyuan Xu

IET Comput. Digit. Tech., 2016

2015

Design of a novel RTD-based three-variable universal logic gate.

Maoqun Yao, Kai Yang, Congyuan Xu, Jizhong Shen

Frontiers Inf. Technol. Electron. Eng., 2015

Function Synthesis Algorithm of RTD-Based Universal Threshold Logic Gate.

Maoqun Yao, Kai Yang, Congyuan Xu, Jizhong Shen

J. Appl. Math., 2015