Craig Disselkoen

Orcid: 0000-0003-4358-2963

According to our database1, Craig Disselkoen authored at least 19 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Cedar: A New Language for Expressive, Fast, Safe, and Analyzable Authorization (Extended Version).
CoRR, 2024

2023
MSWasm: Soundly Enforcing Memory-Safe Execution of Unsafe Code.
Proc. ACM Program. Lang., January, 2023

2022
Memory Safety for Today's Languages and Architectures
PhD thesis, 2022

MSWasm: Soundly Enforcing Memory-Safe Execution of Unsafe Code.
CoRR, 2022

SoK: Practical Foundations for Software Spectre Defenses.
Proceedings of the 43rd IEEE Symposium on Security and Privacy, 2022

2021
Automatically eliminating speculative leaks from cryptographic code with blade.
Proc. ACM Program. Lang., 2021

SoK: Practical Foundations for Spectre Defenses.
CoRR, 2021

Swivel: Hardening WebAssembly against Spectre.
Proceedings of the 30th USENIX Security Symposium, 2021

Tutorial: Sandboxing (unsafe) C code with RLBox.
Proceedings of the IEEE Secure Development Conference, 2021

2020
The Road to Less Trusted Code: Lowering the Barrier to In-Process Sandboxing.
login Usenix Mag., 2020

Retrofitting Fine Grain Isolation in the Firefox Renderer (Extended Version).
CoRR, 2020

Retrofitting Fine Grain Isolation in the Firefox Renderer.
Proceedings of the 29th USENIX Security Symposium, 2020

Constant-time foundations for the new spectre era.
Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2020

2019
Towards Constant-Time Foundations for the New Spectre Era.
CoRR, 2019

The Code That Never Ran: Modeling Attacks on Speculative Evaluation.
Proceedings of the 2019 IEEE Symposium on Security and Privacy, 2019

Position Paper: Progressive Memory Safety for WebAssembly.
Proceedings of the 8th International Workshop on Hardware and Architectural Support for Security and Privacy, 2019

2018
Browser history re: visited.
Proceedings of the 12th USENIX Workshop on Offensive Technologies, 2018

2017
Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX.
Proceedings of the 26th USENIX Security Symposium, 2017

Improved Performance of Gene Set Analysis on Genome-Wide Transcriptomics Data when Using Gene Activity State Estimates.
Proceedings of the Biocomputing 2017: Proceedings of the Pacific Symposium, 2017


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