Dean M. Tullsen

Orcid: 0000-0003-3174-9316

Affiliations:
  • University of California, San Diego, USA


According to our database1, Dean M. Tullsen authored at least 153 papers between 1993 and 2023.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2011, "For contributions to the architecture of high-performance processors.".

IEEE Fellow

IEEE Fellow 2009, "For contributions to the architecture of multithreaded and high-performance processors".

Timeline

Legend:

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Links

Online presence:

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Bibliography

2023
NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems.
Proceedings of the 32nd USENIX Security Symposium, 2023

Half&Half: Demystifying Intel's Directional Branch Predictors for Fast, Secure Partitioned Execution.
Proceedings of the 44th IEEE Symposium on Security and Privacy, 2023

Going beyond the Limits of SFI: Flexible and Secure Hardware-Assisted In-Process Isolation with HFI.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
Mitigating Speculative Execution Attacks via Context-Sensitive Fencing.
IEEE Des. Test, 2022

SecSMT: Securing SMT Processors against Contention-Based Covert Channels.
Proceedings of the 31st USENIX Security Symposium, 2022

EVAX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021
Automatically eliminating speculative leaks from cryptographic code with blade.
Proc. ACM Program. Lang., 2021

Agon: A Scalable Competitive Scheduler for Large Heterogeneous Systems.
CoRR, 2021

Not All Features Are Equal: Discovering Essential Features for Preserving Prediction Privacy.
Proceedings of the WWW '21: The Web Conference 2021, 2021

Swivel: Hardening WebAssembly against Spectre.
Proceedings of the 30th USENIX Security Symposium, 2021

I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
Temperature-Aware DRAM Cache Management - Relaxing Thermal Constraints in 3-D Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Principled Approach to Learning Stochastic Representations for Privacy in Deep Neural Inference.
CoRR, 2020

Constant-time foundations for the new spectre era.
Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2020

Packet Chasing: Spying on Network Packets over a Cache Side-Channel.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Shredder: Learning Noise Distributions to Protect Inference Privacy.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management.
IEEE Micro, 2019

Shredder: Learning Noise to Protect Privacy with Partial DNN Inference on the Edge.
CoRR, 2019

Platform-Agnostic Learning-Based Scheduling.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Deciphering Predictive Schedulers for Heterogeneous-ISA Multicore Architectures.
Proceedings of the 10th International Workshop on Programming Models and Applications for Multicores and Manycores, 2019

Composite-ISA Cores: Enabling Multi-ISA Heterogeneity Using a Single ISA.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Understanding the Impact of Socket Density in Density Optimized Servers.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Mobilizing the Micro-Ops: Exploiting Context Sensitive Decoding for Security and Energy Efficiency.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Virtual Melting Temperature: Managing Server Load to Minimize Cooling Overhead with Phase Change Materials.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Reliability-Aware Data Placement for Heterogeneous Memory Architecture.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Thermal Time Shifting: Decreasing Data Center Cooling Costs with Phase-Change Materials.
IEEE Internet Comput., 2017

Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX.
Proceedings of the 26th USENIX Security Symposium, 2017

Co-locating and concurrent fine-tuning MapReduce applications on microservers for energy efficiency.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
The case for colocation of high performance computing workloads.
Concurr. Comput. Pract. Exp., 2016

Horton Tables: Fast Hash Tables for In-Memory Data-Intensive Computing.
Proceedings of the 2016 USENIX Annual Technical Conference, 2016

Reliability and Performance Trade-off Study of Heterogeneous Memories.
Proceedings of the Second International Symposium on Memory Systems, 2016

HIPStR: Heterogeneous-ISA Program State Relocation.
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

2015
Heterogeneous Computing [Guest editors' introduction].
IEEE Micro, 2015

The CRISP performance model for dynamic voltage and frequency scaling in a GPGPU.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Thermal time shifting: leveraging phase change materials to reduce cooling costs in warehouse-scale computers.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014
2014 International Symposium on Computer Architecture Influential Paper Award; 2014 Maurice Wilkes Award Given to Ravi Rajwar.
IEEE Micro, 2014

Resistive Computation: A Critique.
IEEE Comput. Archit. Lett., 2014

A comparison of core power gating strategies implemented in modern hardware.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Modeling and analysis of Phase Change Materials for efficient thermal management.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

CDTT: Compiler-generated data-triggered threads.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Enabling Dynamic Heterogeneity Through Core-on-Core Stacking.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Multithreading Architecture
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01738-4, 2013

Thread Row Buffers: Improving Memory Performance Isolation and Throughput in Multiprogrammed Environments.
IEEE Trans. Computers, 2013

The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing.
ACM Trans. Archit. Code Optim., 2013

Load-balanced pipeline parallelism.
Proceedings of the International Conference for High Performance Computing, 2013

Low-current probabilistic writes for power-efficient STT-RAM caches.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs.
Proceedings of the International Green Computing Conference, 2013

2012
Eliminating Redundant Computation and Exposing Parallelism through Data-Triggered Threads.
IEEE Micro, 2012

Underclocked Software Prefetching: More Cores, Less Energy.
IEEE Micro, 2012

Redefining the Role of the CPU in the Era of CPU-GPU Integration.
IEEE Micro, 2012

Fast cost efficient designs by building upon the plackett and burman method.
Proceedings of the ACM SIGMETRICS/PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems, 2012

Efficient system design using the Statistical Analysis of Architectural Bottlenecks methodology.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Software data-triggered threads.
Proceedings of the 27th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2012

Hot peripheral thermal management to mitigate cache temperature variation.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Managing distributed UPS energy for effective power capping in data centers.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Power-sensitive multithreaded architecture.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Retrospective on "Power-Sensitive Multithreaded Architecture".
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Dynamically heterogeneous cores through 3D resource pooling.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Themis: Energy Efficient Management of Workloads in Virtualized Data Centers.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

Execution migration in a heterogeneous-ISA chip multiprocessor.
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

Coalition threading: combining traditional andnon-traditional parallelism to maximize scalability.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Data Layout for Cache Performance on a Multithreaded Architecture.
Trans. High Perform. Embed. Archit. Compil., 2011

Data-triggered threads: Eliminating redundant computation.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Fast thread migration via cache working set prediction.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Runtime parallelization of legacy code on a transactional memory system.
Proceedings of the High Performance Embedded Architectures and Compilers, 2011

Inter-core prefetching for multicore processors using migrating helper threads.
Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, 2011

2010
Software data spreading: leveraging distributed caches to improve single thread performance.
Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2010

Dynamic workload characterization for power efficient scheduling on CMP systems.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Inter-socket victim cacheing for platform power reduction.
Proceedings of the 28th International Conference on Computer Design, 2010

2009
Fast switching of threads between cores.
ACM SIGOPS Oper. Syst. Rev., 2009

Introduction to the special issue on the 2008 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'08).
SIGARCH Comput. Archit. News, 2009

Guest Editors' Introduction: Top Picks from the 2008 Computer Architecture Conferences.
IEEE Micro, 2009

Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors.
Proceedings of the Eleventh International Joint Conference on Measurement and Modeling of Computer Systems, 2009

McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Reducing peak power with a table-driven adaptive processor core.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Creating artificial global history to improve branch prediction accuracy.
Proceedings of the 23rd international conference on Supercomputing, 2009

Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading.
Proceedings of the PACT 2009, 2009

2008
Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices.
IEEE Trans. Parallel Distributed Syst., 2008

Editorial.
ACM Trans. Archit. Code Optim., 2008

Introduction to the special issue on the 2007 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'07).
SIGARCH Comput. Archit. News, 2008

Holistic Design of Multiple-Core Architectures.
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008

The shared-thread multiprocessor.
Proceedings of the 22nd Annual International Conference on Supercomputing, 2008

Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Accurate branch prediction for short threads.
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

2007
Editorial: Special Section on CMP Architectures.
IEEE Trans. Parallel Distributed Syst., 2007

Introduction to the special issue on the 2006 workshop on design, analysis, and simulation of chip multiprocessors: (dasCMP'06).
SIGARCH Comput. Archit. News, 2007

The architecture of Efficient Multi-Core Processors: A Holistic Approach.
Adv. Comput., 2007

Proximity-aware directory-based coherence for multi-core processor architectures.
Proceedings of the SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2007

HCW Keynote Address Holistic Design of Multi-Core Architectures.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Accelerating and Adapting Precomputation Threads for Effcient Prefetching.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2006
Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Speculative Code Value Specialization Using the Trace Cache Fill Unit.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Conjoining soft-core FPGA processors.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Application-specific customization of parameterized FPGA soft-core processors.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework.
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

Core architecture optimization for heterogeneous chip multiprocessors.
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005
Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05).
SIGARCH Comput. Archit. News, 2005

Architecture-Level Power Optimization - What Are the Limits?
J. Instr. Level Parallelism, 2005

Heterogeneous Chip Multiprocessors.
Computer, 2005

The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best.
IEEE Comput. Archit. Lett., 2005

Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices.
Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005

Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

A Tree Based Router Search Engine Architecture with Single Port Memories.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Multithreaded Value Prediction.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

An Event-Driven Multithreaded Dynamic Optimization Framework.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2004
Introduction.
ACM Trans. Archit. Code Optim., 2004

Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Conjoined-Core Chip Multiprocessing.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Control Flow Optimization Via Dynamic Reconvergence Prediction.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

Clustered Multithreaded Architectures - Pursuing both IPC and Cycle Time.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003
Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures.
IEEE Comput. Archit. Lett., 2003

Exploring the Potential of Architecture-Level Power Optimizations.
Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Initial Observations of the Simultaneous Multithreading Pentium 4 Processor.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

The Effect of Compiler Optimizations on Pentium 4 Power Consumption.
Proceedings of the 7th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7 2003), 2003

2002
Symbiotic jobscheduling with priorities for a simultaneous multithreading processor.
Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2002

Compiling for instruction cache performance on a multithreaded architecture.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Pointer cache assisted prefetching.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Quantifying Instruction Criticality.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001
Runtime identification of cache conflict misses: The adaptive miss buffer.
ACM Trans. Comput. Syst., 2001

Handling long-latency loads in a simultaneous multithreading processor.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Reducing power with dynamic critical path information.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Dynamic speculative precomputation.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Speculative precomputation: long-range prefetching of delinquent loads.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

Dynamic Prediction of Critical Path Instructions.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

2000
Limits of task-based parallelism in irregular applications.
SIGARCH Comput. Archit. News, 2000

Symbiotic Jobscheduling for a Simultaneous Multithreading Processor.
Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000

1999
Software-Directed Register Deallocation for Simultaneous Multithreaded Processors.
IEEE Trans. Parallel Distributed Syst., 1999

Tuning Compiler Optimizations for Simultaneous Multithreading.
Int. J. Parallel Program., 1999

ILP versus TLP on SMT.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1999

Hardware Identification of Cache Conflict Misses.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

Storageless Value Prediction Using Prior Register Values.
Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

Selective Value Prediction.
Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

Classifying load and store instructions for memory renaming.
Proceedings of the 13th international conference on Supercomputing, 1999

Instruction Recycling on a Multiple-Path Processor.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

Multithreaded Execution Architecture and Compilation.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998
Threaded Multiple Path Execution.
Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

Simultaneous Multithreading: Maximizing On-Chip Parallelism.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Retrospective: Simultaneous Multithreading: Maximizing On-Chip Parallelism.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

1997
Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading.
ACM Trans. Comput. Syst., 1997

Simultaneous multithreading: a platform for next-generation processors.
IEEE Micro, 1997

1996
Simultaneous multithreading.
PhD thesis, 1996

Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor.
Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996

Fellowship - Simulation And Modeling Of A Simultaneous Multithreading Processor.
Proceedings of the 22nd International Computer Measurement Group Conference, 1996

1995
Effective Cache Prefetching on Bus-Based Multiprocessors
ACM Trans. Comput. Syst., 1995

1993
Limitations of Cache Prefetching on a Bus-Based Multiprocessor.
Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993


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