Daichi Tokuda

According to our database, Daichi Tokuda authored at least 3 papers in 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination.

Daichi Tokuda, Shinya Takamaeda-Yamazaki

ACM Trans. Reconfigurable Technol. Syst., June, 2025

MVDRAM: Enabling GeMV Execution in Unmodified DRAM for Low-Bit LLM Acceleration.

Tatsuya Kubo, Daichi Tokuda, Tomoya Nagatani, Masayuki Usui, Lei Qu, Ting Cao, Shinya Takamaeda-Yamazaki

CoRR, March, 2025

PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM.

Tatsuya Kubo, Daichi Tokuda, Lei Qu, Ting Cao, Shinya Takamaeda-Yamazaki

IEEE Comput. Archit. Lett., 2025