Shinya Takamaeda-Yamazaki

According to our database1, Shinya Takamaeda-Yamazaki authored at least 37 papers between 2010 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS.
J. Solid-State Circuits, 2019

FPGA-Based Annealing Processor with Time-Division Multiplexing.
IEICE Transactions, 2019

Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks.
IEICE Transactions, 2019

A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators.
Proceedings of the 2019 Seventh International Symposium on Computing and Networking, 2019

Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band.
Proceedings of the 2019 Digital Image Computing: Techniques and Applications, 2019

DeltaNet: Differential Binary Neural Network.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA.
Microprocess. Microsystems, 2018

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.
J. Solid-State Circuits, 2018

A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing.
IEICE Transactions, 2018

Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing.
Complexity, 2018

Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions.
Proceedings of the IEEE Visual Communications and Image Processing, 2018

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware.
Proceedings of the International Conference on Field-Programmable Technology, 2018

2017
Quantization Error-Based Regularization in Neural Networks.
Proceedings of the Artificial Intelligence XXXIV, 2017

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017

A Time-Division Multiplexing Ising Machine on FPGAs.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Accelerating deep learning by binarized hardware.
Proceedings of the 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2017

2016
Performance Optimization of Light-Field Applications on GPU.
IEICE Transactions, 2016

CPRtree: A Tree-Based Checkpointing Architecture for Heterogeneous FPGA Computing.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

2015
Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs.
IEICE Transactions, 2015

Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators.
IEICE Transactions, 2015

A CGRA-Based Approach for Accelerating Convolutional Neural Networks.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

A Distributed Memory Based Embedded CGRA for Accelerating Stencil Computations.
Proceedings of the Third International Symposium on Computing and Networking, 2015

Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
A framework for efficient rapid prototyping by virtually enlarging FPGA resources.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Ultrasmall: The smallest MIPS soft processor.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2012
Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations.
Proceedings of the Third International Conference on Networking and Computing, 2012

ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
An FPGA-based scalable simulation accelerator for tile architectures.
SIGARCH Computer Architecture News, 2011

2010
Smart Core System for Dependable Many-Core Processor with Multifunction Routers.
Proceedings of the First International Conference on Networking and Computing, 2010


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