Daiguo Xu

Orcid: 0000-0003-1461-599X

According to our database1, Daiguo Xu authored at least 10 papers between 2018 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A 12bit 250 MS/s 5.43fJ/conversion-step SAR ADC with adaptive asynchronous logic in 28 nm CMOS.
Microelectron. J., 2022

2021
A Noise Reduction 12-bit 125-MSPS SAR ADC with Modified Asynchronous Logic Regulation Technique.
J. Circuits Syst. Comput., 2021

2020
A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique.
J. Circuits Syst. Comput., 2020

Low-Voltage High-Linearity Differential Input Buffer with CurrentAmplifier Feed-Forward Compensation for High-Speed ADCs.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

2019
A Linearity-Enhanced 10-Bit 160-MS/s SAR ADC With Low-Noise Comparator Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Rapid calibration of bits weights error for high-resolution successive approximation register ADC.
IET Circuits Devices Syst., 2019

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique.
IEICE Electron. Express, 2019

2018
A Linearity-Improved 8-bit 320-MS/s SAR ADC With Metastability Immunity Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A System-Level Correction SAR ADC with Noise-Tolerant Technique.
J. Circuits Syst. Comput., 2018

A 10-bit 1.2 GS/s 45 mW time-interleaved SAR ADC with background calibration.
IEICE Electron. Express, 2018


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