Ning Ning
Orcid: 0000-0001-7893-1428Affiliations:
- University of Electronic Science and Technology of China, State Key Laboratory of Electronic Thin Films and Integrated Devices, Chengdu, China
According to our database1,
Ning Ning
authored at least 50 papers
between 2013 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Floating-Point Approximation Enabling Cost-Effective and High-Precision Digital Implementation of FitzHugh-Nagumo Neural Networks.
IEEE Trans. Biomed. Circuits Syst., April, 2024
2023
A 0.053 mm<sup>2</sup> 10-bit 10-ks/s 40-nW SAR ADC with pseudo single ended switching procedure for bio-related applications.
Microelectron. J., September, 2023
A 3-5 GHz, 108fs-RMS jitter, clock receiver circuit for time-interleaved ADCs with a sampling rate of 4 GS/s.
Microelectron. J., September, 2023
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
A programmable analog front-end with independent biasing technique for ECG signal acquisition.
Microelectron. J., 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
A Programmable High-Voltage Pulse Transmitter Circuit for 3-D Miniature Ultrasound Probes.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
An Ultra-Low Specific On-Resistance LDMOS With Segmented LOCOS In 0.18 μm BCD Process Platform.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
A Co-Designed Neuromorphic Chip With Compact (17.9K F<sup>2</sup>) and Weak Neuron Number-Dependent Neuron/Synapse Modules.
IEEE Trans. Biomed. Circuits Syst., December, 2022
A Code-Recombination Algorithm-Based ADC With Feature Extraction for WBSN Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A 12bit 250 MS/s 5.43fJ/conversion-step SAR ADC with adaptive asynchronous logic in 28 nm CMOS.
Microelectron. J., 2022
A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration.
IEEE J. Solid State Circuits, 2022
2021
A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A +0.44°C/-0.4°C Inaccuracy Temperature Sensor With Multi-Threshold MOSFET-Based Sensing Element and CMOS Thyristor-Based VCO.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Direct training of hardware-friendly weight binarized spiking neural network with surrogate gradient learning towards spatio-temporal event-based dynamic data recognition.
Neurocomputing, 2021
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
A Second-Order Passive Noise-Shaping SAR ADC Using the LMS-Based Mismatch Calibration.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst., 2020
A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
A second-order noise-shaping SAR ADC with error-feedback structure and data weighted averaging.
Microelectron. J., 2020
Switching sequence optimization for gradient errors compensation in the current-steering DAC design.
Microelectron. J., 2020
Microelectron. J., 2020
STBNN: Hardware-friendly spatio-temporal binary neural network with high pattern recognition accuracy.
Neurocomputing, 2020
Biomed. Signal Process. Control., 2020
A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors.
IEEE Access, 2020
A 10-Bit Fully-Predictive ADC with Code-Recombination Algorithm in Transducing Sensor Node Signals.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Microelectron. J., 2019
A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters.
J. Circuits Syst. Comput., 2019
J. Circuits Syst. Comput., 2019
A Neuromorphic-Hardware Oriented Bio-Plausible Online-Learning Spiking Neural Network Model.
IEEE Access, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Access, 2018
IEEE Access, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2015
A Supply Voltage and Temperature Variation-Tolerant Relaxation Oscillator for Biomedical Systems Based on Dynamic Threshold and Switched Resistors.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Multiscaling coefficients Technique for gain error Background Calibration in Pipelined ADC.
J. Circuits Syst. Comput., 2014
J. Circuits Syst. Comput., 2014
IEICE Electron. Express, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013