Daniel Kucharski

Orcid: 0009-0006-1724-4871

According to our database1, Daniel Kucharski authored at least 12 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

Online presence:

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Bibliography

2023
Multi-population Algorithm Using Surrogate Models and Different Training Plans.
Proceedings of the Artificial Intelligence and Soft Computing, 2023

2021
Towards Sneaking as a Playful Input Modality for Virtual Environments.
Proceedings of the IEEE Virtual Reality and 3D User Interfaces, 2021

2020
Development of a High Fidelity Simulator for Generalised Photometric Based Space Object Classification using Machine Learning.
CoRR, 2020

2014
Attitude and Spin Period of Space Debris Envisat Measured by Satellite Laser Ranging.
IEEE Trans. Geosci. Remote. Sens., 2014

Spin Axis Precession of LARES Measured by Satellite Laser Ranging.
IEEE Geosci. Remote. Sens. Lett., 2014

2010
The Impact of Solar Irradiance on AJISAI's Spin Period Measured by the Graz 2-kHz SLR System.
IEEE Trans. Geosci. Remote. Sens., 2010

10Gb/s 15mW optical receiver with integrated Germanium photodetector and hybrid inductor peaking in 0.13µm SOI CMOS technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Gravity Probe-B: New Methods to Determine Spin Parameters From kHz SLR Data.
IEEE Trans. Geosci. Remote. Sens., 2009

40Gb/s optical active cable using monolithic transceivers implemented in silicon photonics enabled 0.13-µm SOI CMOS Technology.
Proceedings of the 2009 IEEE Hot Chips 21 Symposium (HCS), 2009

2007
A Fully Integrated 4 × 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 µm CMOS SOI Technology.
IEEE J. Solid State Circuits, 2007

2006
2.5 V 43-45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-Voltage Logic Family.
IEEE J. Solid State Circuits, 2006

A Fully Integrated 20-Gb/s Optoelectronic Transceiver Implemented in a Standard 0.13- $\mu{\hbox {m}}$ CMOS SOI Technology.
IEEE J. Solid State Circuits, 2006


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