Dantu Nandini Devi

According to our database, Dantu Nandini Devi authored at least 10 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

Meta-Heuristic Optimization for Designing Error Diluted Weight Stationary Approximate Systolic Array Architecture.

Dantu Nandini Devi, Bindu G. Gowda, Madhav Rao

Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

Design of Hardware-Efficient Inexact Multiplier Using Evolutionary Algorithm Factored by Multi-Variate Approximation.

Dantu Nandini Devi, Saketh Gajawada, Madhav Rao

Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

LibApprox: A Comprehensive Library for Performance Efficient Approximate Circuits.

D. V. Bhargav, Dantu Nandini Devi, Rachana Kaparthi, Madhav Rao

Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

Precision-Factored Systolic Arrays: Balancing Accuracy and Efficiency in Floating-Point Computations for CNNs.

Dantu Nandini Devi, Madhav Rao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

OEDASA: Optimization Enabled Error-Diluted Approximate Systolic Array Design for an Image Processing Application.

Dantu Nandini Devi, Gandi Ajay Kumar, Bindu G. Gowda, Madhav Rao

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

MOHSKM: Meta-Heuristic Optimization Driven Hardware-Efficient Heterogeneous-Split Karatsuba Multipliers for Large-Bit Operations.

Saketh Gajawada, Dantu Nandini Devi, Madhav Rao

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

PSO Optimized Design of Error Balanced Weight Stationary Systolic Array Architecture for CNN.

Dantu Nandini Devi, Gandi Ajay Kumar, Bindu G. Gowda, Madhav Rao

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Performance-Aware Design of Approximate Integrated MAC Factored Systolic Array Accelerators.

Dantu Nandini Devi, Gandi Ajay Kumar, Bindu G. Gowda, Madhav Rao

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Integrated MAC-based Systolic Arrays: Design and Performance Evaluation.

Dantu Nandini Devi, Gandi Ajay Kumar, Bindu G. Gowda, Madhav Rao

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

HAHMF: Heuristic-Augmented Asymmetric Heterogeneous Splitting for Hardware Efficient Multipliers Framework.

Saketh Gajawada, Dantu Nandini Devi, Madhav Rao

Proceedings of the 27th Euromicro Conference on Digital System Design, 2024