David Borggreve

According to our database1, David Borggreve authored at least 9 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
A 0.8-V Fully Differential Amplifier with 80-dB DC Gain and 8-GHz GBW in 22-nm FDSOI CMOS Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A FeFET In-Memory-Computing Core with Offset Cancellation for Mitigating Computational Errors.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
A Dynamic Charge-Transfer-Based Crossbar with Low Sensitivity to Parasitic Wire-Resistance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A 0.8-V, 2.88-GHz Double-Tail Latched Comparator in 22-nm FDSOI CMOS Technology.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

Impact of Parasitic Wire Resistance on Accuracy and Size of Resistive Crossbars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Quantization Considerations of Dense Layers in Convolutional Neural Networks for Resistive Crossbar Implementation.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

2019
A 0.8 V Low-Power 3rd order Sigma-Delta Modulator in 22 nm FDSOI CMOS Process for Sensor Interfaces.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

2018
A low power, offset compensated, CMOS only bandgap reference in 22 nm FD-SOI technology.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

2017
Low-voltage low-distortion sampling switch design in 22 nm FD-SOI CMOS technology.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017


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