Ralf Brederlow

  • Technical University Munich, Germany

According to our database1, Ralf Brederlow authored at least 24 papers between 2001 and 2021.

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PhD thesis 


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On csauthors.net:


Towards Easy-to-Use Bacteria Sensing: Modeling and Simulation of a New Environmental Impedimetric Biosensor in Fluids.
Sensors, 2021

Impact of Parasitic Wire Resistance on Accuracy and Size of Resistive Crossbars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A CMOS Temperature Stabilized 2-D Mechanical Stress Sensor With 11-bit Resolution.
IEEE J. Solid State Circuits, 2020

Quantization Considerations of Dense Layers in Convolutional Neural Networks for Resistive Crossbar Implementation.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

A CMOS Temperature Stabilized 2-Dimensional Mechanical Stress Sensor with 11-bit Resolution.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Integrated multipurpose analog front-end for electrochemical ISFET sensors.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications.
IEEE J. Solid State Circuits, 2018

A 92.1% efficient DC-DC converter for ultra-low power microcontrollers with fast wake-up.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Towards Side-Channel Secure Firmware Updates - A Minimalist Anomaly Detection Approach.
Proceedings of the Foundations and Practice of Security - 9th International Symposium, 2016

Session 27 overview: Physical sensors: Imagers, MEMS, medical and displays subcommittee.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Risk management in embedded devices using metering applications as example.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014

An Ultra Low Power Bandgap Operational at Supply From 0.75 V.
IEEE J. Solid State Circuits, 2012

An ultra low power bandgap operational at supply as low as 0.75V.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A Complementary Switched MOSFET Architecture for the 1/f Noise Reduction in Linear Analog CMOS ICs.
IEEE J. Solid State Circuits, 2007

Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.
Proceedings of the IFIP VLSI-SoC 2007, 2007

An Integrated Gravimetric FBAR Circuit for Operation in Liquids Using a Flip-Chip Extended 0.13μm CMOS Technology.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A low-power true random number generator using random telegraph noise of single oxide-traps.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 24x16 CMOS-Based Chronocoulometric DNA Microarray.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Effects of inhomogeneous negative bias temperature stress on p-channel MOSFETs of analog and RF circuits.
Microelectron. Reliab., 2005

A Mixed-Signal Design Roadmap.
IEEE Des. Test Comput., 2001

An efficient and precise design method to optimize device areas in mismatch and flicker-noise sensitive analog circuits.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001