Ralf Brederlow

According to our database1, Ralf Brederlow
  • authored at least 14 papers between 2001 and 2018.
  • has a "Dijkstra number"2 of five.

Timeline

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Bibliography

2018
A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications.
J. Solid-State Circuits, 2018

2017
A 92.1% efficient DC-DC converter for ultra-low power microcontrollers with fast wake-up.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Towards Side-Channel Secure Firmware Updates - A Minimalist Anomaly Detection Approach.
Proceedings of the Foundations and Practice of Security - 9th International Symposium, 2016

2015
Session 27 overview: Physical sensors: Imagers, MEMS, medical and displays subcommittee.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems.
IEEE Trans. VLSI Syst., 2014

Risk management in embedded devices using metering applications as example.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014

2012
An Ultra Low Power Bandgap Operational at Supply From 0.75 V.
J. Solid-State Circuits, 2012

2011
An ultra low power bandgap operational at supply as low as 0.75V.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2007
CMOS-Based Biosensor Arrays
CoRR, 2007

Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.
Proceedings of the IFIP VLSI-SoC 2007, 2007

An Integrated Gravimetric FBAR Circuit for Operation in Liquids Using a Flip-Chip Extended 0.13μm CMOS Technology.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
Effects of inhomogeneous negative bias temperature stress on p-channel MOSFETs of analog and RF circuits.
Microelectronics Reliability, 2005


2001
A Mixed-Signal Design Roadmap.
IEEE Design & Test of Computers, 2001


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