David Clarino

According to our database, David Clarino authored at least 6 papers between 2023 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Leveraging Different Boolean Function Decompositions to Reduce T-Count in LUT-Based Quantum Circuit Synthesis.

David Clarino, Naoya Asada, Atsushi Matsuo, Shigeru Yamashita

IEICE Trans. Inf. Syst., 2025

Reducing T-Count in Quantum Circuits Using Alternate Forms of the Relative Phase Toffoli Gate.

David Clarino, Shohei Kuroda, Shigeru Yamashita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025

A Decomposition Method for MCT Gates Considering T-depth of Each Qubit.

Zanhe Qi, Kouki Hirono, David Clarino, Shigeru Yamashita

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

2024

Utilizing Don't-Cares to Minimize CNOTs in Synthesizing NNA Compliant Quantum Circuits.

David Clarino, Kyouhei Seino, Atsushi Matsuo, Shigeru Yamashita

Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024

2023

Using S Gates and Relative Phase Toffoli Gates to Improve T-Count in Quantum Boolean Circuits.

David Clarino, Shohei Kuroda, Shigeru Yamashita

Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

Optimizing LUT-Based Quantum Circuit Synthesis Using Relative Phase Boolean Operations.

David Clarino, Naoya Asada, Shigeru Yamashita

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023