Shigeru Yamashita

According to our database1, Shigeru Yamashita authored at least 101 papers between 1995 and 2022.

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Bibliography

2022
Approximating stochastic numbers to reduce latency.
it Inf. Technol., 2022

Optimization of Quantum Boolean Circuits by Relative-Phase Toffoli Gates.
Proceedings of the Reversible Computation - 14th International Conference, 2022

2021
Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution.
Integr., 2021

A Multiply Accumulator for Stochastic Numbers Without Scaling Errors.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Triple-Rail Stochastic Number and Its Applications.
Proceedings of the 18th International SoC Design Conference, 2021

Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Minimization of Routing Area in MEDA Biochips.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Efficient Methods to Generate Constant SNs with Considering Trade-Off between Error and Overhead and Its Evaluation.
IEICE Trans. Inf. Syst., 2020

Editorial for the special issue on disruptive computing technologies.
CCF Trans. High Perform. Comput., 2020

Reducing T-count When Decomposing Many MPMCT Gates Simultaneously.
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Optimization of Fluid Loading on Programmable Microfluidic Devices for Bio-protocol Execution.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based Biochips.
ACM Trans. Design Autom. Electr. Syst., 2019

Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Mapping a Quantum Circuit to 2D Nearest Neighbor Architecture by Changing the Gate Order.
IEICE Trans. Inf. Syst., 2019

Compaction of Topological Quantum Circuits by Modularization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Reducing the Overhead of Stochastic Number Generators Without Increasing Error.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

An Efficient Method for Quantum Circuit Placement Problem on a 2-D Grid.
Proceedings of the Reversible Computation - 11th International Conference, 2019

Maximum Error-Aware Design of Approximate Array Multipliers.
Proceedings of the 2019 International SoC Design Conference, 2019

Reducing the Overhead of Mapping Quantum Circuits to IBM Q System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Logical Qubit Layout Problem for ICM Representation.
J. Inf. Process., 2018

Quantum Circuit Optimization by Changing the Gate Order for 2D Nearest Neighbor Architectures.
Proceedings of the Reversible Computation - 10th International Conference, 2018

2017
Microfluidic Biochips: Bridging Biochemistry with Computer Science and Engineering (NII Shonan Meeting 2017-1).
NII Shonan Meet. Rep., 2017

A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Stochastic Number Generation with the Minimum Inputs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Reduction of Quantum Cost by Making Temporary Changes to the Function.
IEICE Trans. Inf. Syst., 2017

2016
A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders.
CoRR, 2016

Quantum Query Complexity of Almost All Functions with Fixed On-set Size.
Comput. Complex., 2016

ILP-based Synthesis for Sample Preparation Applications on Digital Microfluidic Biochips.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Stochastic Number Generation with Few Inputs.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Design of Microfluidic Biochips: Connecting Algorithms and Foundations of Chip Design to Biochemistry and the Life Sciences.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A pre-optimization technique to generate initial reversible circuits with low quantum cost.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A systematic methodology for design and analysis of approximate array multipliers.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A general testing method for digital microfluidic biochips under physical constraints.
Proceedings of the 2015 IEEE International Test Conference, 2015

Testing of digital microfluidic biochips with arbitrary layouts.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
An Energy-Efficient Patchable Accelerator and Its Design Methods.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2D Qubit Layout Optimization for Topological Quantum Computation.
Proceedings of the Reversible Computation - 6th International Conference, 2014

Better-Than-DMR Techniques for Yield Improvement.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

A logic integrated optimal pin-count design for digital microfluidic biochips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A network-flow-based optimal sample preparation algorithm for digital microfluidic biochips.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication.
IEICE Trans. Inf. Syst., 2013

Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Selective Check of Data-Path for Effective Fault Tolerance.
IEICE Trans. Inf. Syst., 2013

On the Error Resiliency of Combinational Logic Cells - Implications for Nano-based Digital Design.
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Synthesis of Semi-Classical Quantum Circuits.
J. Multiple Valued Log. Soft Comput., 2012

Quantum Walks on the Line with Phase Parameters.
IEICE Trans. Inf. Syst., 2012

Reconstructing Strings from Substrings with Quantum Queries.
Proceedings of the Algorithm Theory - SWAT 2012, 2012

A redundant wire addition method for Patchable Accelerator.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

An Optimization Problem for Topological Quantum Computation.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

On error tolerance and Engineering Change with Partially Programmable Circuits.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
An efficient conversion of quantum circuits to a linear nearest neighbor architecture.
Quantum Inf. Comput., 2011

Changing the Gate Order for Optimal LNN Conversion.
Proceedings of the Reversible Computation - Third International Workshop, 2011

An efficient algorithm for constructing a Sequence Binary Decision Diagram representing a set of reversed sequences.
Proceedings of the 2011 IEEE International Conference on Granular Computing, 2011

2010
Fast equivalence - checking for quantum circuits.
Quantum Inf. Comput., 2010

2009
Synthesis of quantum circuits for d-level systems by using cosine-sine decomposition.
Quantum Inf. Comput., 2009

Multi-Party Quantum Communication Complexity with Routed Messages.
IEICE Trans. Inf. Syst., 2009

Average/Worst-Case Gap of Quantum Query Complexities by On-Set Size
CoRR, 2009

2008
DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Functional Unit with Small Variety of Highly Reliable Cells.
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008

Quantum Query Complexity of Boolean Functions with Small On-Sets.
Proceedings of the Algorithms and Computation, 19th International Symposium, 2008

Polynomial-Time Construction of Linear Network Coding.
Proceedings of the Automata, Languages and Programming, 35th International Colloquium, 2008

An efficient verification of quantum circuits under a practical restriction.
Proceedings of 8th IEEE International Conference on Computer and Information Technology, 2008

2007
Improved algorithms for quantum identification of Boolean oracles.
Theor. Comput. Sci., 2007

Robust Quantum Algorithms Computing OR with epsilon-Biased Oracles.
IEICE Trans. Inf. Syst., 2007

Unbounded-Error Classical and Quantum Communication Complexity.
Proceedings of the Algorithms and Computation, 18th International Symposium, 2007

Unbounded-Error One-Way Classical and Quantum Communication Complexity.
Proceedings of the Automata, Languages and Programming, 34th International Colloquium, 2007

A practical framework to utilize quantum search.
Proceedings of the IEEE Congress on Evolutionary Computation, 2007

A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Quantum lower bounds for the Goldreich-Levin problem.
Inf. Process. Lett., 2006

An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

(4, 1)-Quantum Random Access Coding Does Not Exist.
Proceedings of the Proceedings 2006 IEEE International Symposium on Information Theory, 2006

Quantum Network Coding.
Proceedings of the Complexity of Boolean Functions, 12.03. - 17.03.2006, 2006

Robust Quantum Algorithms with <i>epsilon</i>-Biased Oracles.
Proceedings of the Computing and Combinatorics, 12th Annual International Conference, 2006

A transduction-based framework to synthesize RSFQ circuits.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Quantum Sampling for Balanced Allocations.
IEICE Trans. Inf. Syst., 2005

Reconfigurable 1-Bit Processor Array with Reduced Wirng Area.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

Event-oriented computing with reconfigurable platform.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Quantum Identification of Boolean Oracles.
Proceedings of the STACS 2004, 2004

SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

SPFD-based one-to-many rewiring.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003
Efficient Algorithms for NMR Quantum Computers with Small Qubits.
New Gener. Comput., 2003

Transformation Rules for CNOT-based Quantum Circuits and Their Applications.
New Gener. Comput., 2003

2002
Transformation rules for designing CNOT-based quantum circuits.
Proceedings of the 39th Design Automation Conference, 2002

2000
SPFD: A new method to express functional flexibility.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation.
Proceedings of ASP-DAC 2000, 2000

1999
An Integrated Approach for Synthesizing LUT Networks.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions.
Proceedings of the 1998 Design, 1998

New Methods to Find Optimal Non-Disjoint Bi-Decompositions.
Proceedings of the ASP-DAC '98, 1998

1997
Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1996
Optimization methods for look-up table-type FPGAs based on permissible functions.
Systems and Computers in Japan, 1996

Design of logic circuits with wired-logic utilizing transduction method.
Systems and Computers in Japan, 1996

A new method to express functional permissibilities for LUT based FPGAs and its applications.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995
Optimization methods for lookup-table-based FPGAs using transduction method.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995


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