David Hansquine

According to our database, David Hansquine authored at least 5 papers between 2014 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range.

Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine

IEEE J. Solid State Circuits, 2016

2015

8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range.

Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells.

Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, Keith A. Bowman, David Hansquine

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors.

Keith A. Bowman, Alex Park, Venkat Narayanan, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine

Proceedings of the 2014 International Test Conference, 2014

Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors.

Alex Park, Venkat Narayanan, Keith A. Bowman, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014