Deepak Baranwal

According to our database1, Deepak Baranwal authored at least 1 paper in 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Reliability Enhancement of SoCs Based on Dynamic Memory Access Profiling in Conjunction with PVT Monitoring.
Proceedings of the 28th International Conference on VLSI Design, 2015


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