Dharshak B. S.

According to our database1, Dharshak B. S. authored at least 1 paper in 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A High Performance Gated Voltage Level Translator with Integrated Multiplexer.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018


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