Rahul M. Rao

According to our database1, Rahul M. Rao authored at least 41 papers between 1978 and 2024.

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Bibliography

2024
Late Breaking Results: Scan-Chain Optimization with Constrained Single Linkage Clustering and Geometry-Based Cluster Balancing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2022
Scan Chain Clustering and Optimization with Constrained Clustering and Reinforcement Learning.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

2019
A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2018
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.
IEEE J. Solid State Circuits, 2018

IBM POWER9 circuit design and energy optimization for 14-nm technology.
IBM J. Res. Dev., 2018

Impact of Device Aging on Early Mode Failures in Pulsed Latches.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

A High Performance Gated Voltage Level Translator with Integrated Multiplexer.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017
Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics.
IEEE Trans. Very Large Scale Integr. Syst., 2017

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
FVCAG: A framework for formal verification driven power modeling and verification.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

2015
IBM POWER8 circuit design and energy optimization.
IBM J. Res. Dev., 2015

Virtual logic netlist: Enabling efficient RTL analysis.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2013
Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Extracting device-parameter variations using a single sensitivity-configurable ring oscillator.
Proceedings of the 18th IEEE European Test Symposium, 2013

2011
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Variations: Sources and Characterization.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010
Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Technology-circuit co-design of asymmetric SRAM cells for read stability improvement.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability.
Microelectron. Reliab., 2009

A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry.
IEEE J. Solid State Circuits, 2009

A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Parametric Yield Analysis and Optimization in Leakage Dominated Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2007

2005
Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Power-aware global signaling strategies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Analysis and Optimization of Enhanced MTCMOS Scheme.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Approaches to run-time and standby mode leakage reduction in global buses.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003
Efficient techniques for gate leakage estimation.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Leakage and leakage sensitivity computation for combinational circuits.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies.
Proceedings of the ESSCIRC 2003, 2003

1978
Frequency estimation by linear prediction.
Proceedings of the IEEE International Conference on Acoustics, 1978


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