Rahul M. Rao

According to our database, Rahul M. Rao authored at least 40 papers between 1978 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Scan Chain Clustering and Optimization with Constrained Clustering and Reinforcement Learning.

Naiju Karim Abdul, George Antony, Rahul M. Rao, Suriya T. Skariah

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology.

Rahul M. Rao, Christopher J. Gonzalez, Eric Fluhr, Abraham Mathews, Andrew Bianchi, Daniel Dreps, David Wolpert, Eric Lai, Gerald Strevig, Glen A. Wiedemeier, Philipp Salz, Ryan Kruse

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

Energy Efficiency Boost in the AI-Infused POWER10 Processor.

Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2019

A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits.

Shivani Bathla, Rahul M. Rao, Nitin Chandrachoodan

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.

Christopher J. Gonzalez, Michael S. Floyd, Eric Fluhr, Phillip J. Restle, Daniel Dreps, Michael A. Sperling, Rahul M. Rao, David Hogenmiller, Christos Vezyrtzis, Pierce Chuang, Daniel Lewis, Ricardo Escobar, Vinod Ramadurai, Ryan Kruse, Juergen Pille, Ryan Nett, Pawel Owczarczyk, Joshua Friedrich, Jose Paredes, Timothy Diemoz, Md. Saiful Islam, Donald W. Plass, Paul Muench

IEEE J. Solid State Circuits, 2018

IBM POWER9 circuit design and energy optimization for 14-nm technology.

Eric J. Fluhr, Rahul M. Rao, Howard Smith, Alper Buyuktosunoglu, Ramon Bertran Monfort

IBM J. Res. Dev., 2018

Impact of Device Aging on Early Mode Failures in Pulsed Latches.

Ankur Shukla, Rahul M. Rao, James D. Warnock

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

A High Performance Gated Voltage Level Translator with Integrated Multiplexer.

Dharshak B. S., Rahul M. Rao

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017

Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics.

Sumantra Sarkar, Ayan Biswas, Anindya Sundar Dhar, Rahul M. Rao

IEEE Trans. Very Large Scale Integr. Syst., 2017

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4.

Christopher J. Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul M. Rao, Jose Paredes, Michael S. Floyd, Michael A. Sperling, Ryan Kruse, Vinod Ramadurai, Ryan Nett, Md. Saiful Islam, Juergen Pille, Donald W. Plass

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

FVCAG: A framework for formal verification driven power modeling and verification.

Arun Joseph, Spandana Rachamalla, Rahul M. Rao, Anand Haridass, Pradeep Kumar Nalla

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

2015

IBM POWER8 circuit design and energy optimization.

Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny

IBM J. Res. Dev., 2015

Virtual logic netlist: Enabling efficient RTL analysis.

Spandana Rachamalla, Arun Joseph, Rahul M. Rao, Diwesh Pandey

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2013

Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection.

Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown

IEEE Trans. Very Large Scale Integr. Syst., 2013

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis.

Nagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul M. Rao, Christopher J. Gonzalez

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Extracting device-parameter variations using a single sensitivity-configurable ring oscillator.

Yuma Higuchi, Kenichi Shinkai, Masanori Hashimoto, Rahul M. Rao, Sani R. Nassif

Proceedings of the 18th IEEE European Test Symposium, 2013

2011

SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage.

Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang

IEEE Trans. Very Large Scale Integr. Syst., 2011

Variations: Sources and Characterization.

Aditya Bansal, Rahul M. Rao

Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010

Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise.

Harmander Singh, Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown

IEEE Trans. Very Large Scale Integr. Syst., 2010

Technology-circuit co-design of asymmetric SRAM cells for read stability improvement.

Jae-Joon Kim, Rahul M. Rao, Keunwoo Kim

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability.

Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang

Microelectron. Reliab., 2009

A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry.

Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim

IEEE J. Solid State Circuits, 2009

A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation.

Amlan Ghosh, Rahul M. Rao, Richard B. Brown

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry.

Amlan Ghosh, Richard B. Brown, Rahul M. Rao, Ching-Te Chuang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit.

Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement.

Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits.

Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies.

Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Parametric Yield Analysis and Optimization in Leakage Dominated Technologies.

Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown

IEEE Trans. Very Large Scale Integr. Syst., 2007

2005

Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength.

Harmander Singh Deogun, Dennis Sylvester, Rahul M. Rao, Kevin J. Nowka

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization.

Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.

Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Power-aware global signaling strategies.

Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Analysis and Optimization of Enhanced MTCMOS Scheme.

Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Approaches to run-time and standby mode leakage reduction in global buses.

Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003

Efficient techniques for gate leakage estimation.

Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Leakage and leakage sensitivity computation for combinational circuits.

Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits.

Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies.

Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown

Proceedings of the ESSCIRC 2003, 2003

1978

Frequency estimation by linear prediction.

Leland B. Jackson, Donald W. Tufts, Frank K. Soong, Rahul M. Rao

Proceedings of the IEEE International Conference on Acoustics, 1978