Dina M. Ellaithy

Orcid: 0000-0002-9812-1374

According to our database1, Dina M. Ellaithy authored at least 7 papers between 2017 and 2025.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
Low-Power Low-Complexity 10-Bit Single-Ended SAR ADC in 65-nm CMOS for Biomedical Applications.
Proceedings of the 32nd IEEE International Conference on Electronics, Circuits and Systems, 2025

2022
Dual Channel Multiplier for First-Order Piecewise Approximation for GPU.
J. Circuits Syst. Comput., 2022

Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS Technology.
J. Circuits Syst. Comput., 2022

2021
Design and Implementation of High-Performance Computing Unit for Internet of Things (IoT) Applications.
Proceedings of the International Conference on Microelectronics, 2021

2019
Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for Low-Power 3-D Graphics.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2017
Double Logarithmic Arithmetic Technique for Low-Power 3-D Graphics Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Accurate piecewise uniform approximation logarithmic/antilogarithmic converters for GPU applications.
Proceedings of the 29th International Conference on Microelectronics, 2017


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